I wolud like to use simple oneline code snippet for generating single clock cycle positive pulse

pulse <= '1', '0' after CLK_PERIOD;

However, it is not working (in ghdl simulator at least) is there any chance to improve it? Below, example of tb which only detects first pulse:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb is
end entity;

architecture bench of tb is

    signal clk : std_logic := '0';
    signal pulse : std_logic := '0';
    signal cnt : natural := 0;
    constant CLK_PERIOD : time := 10 ns;


    main: process
        wait until rising_edge(clk);
        pulse <= '1';
        wait until rising_edge(clk);
        pulse <= '0';

        -- oneline pulse generation
        wait until rising_edge(clk);
        pulse <= '1', '0' after CLK_PERIOD;

        wait for 20 ns;
    end process;

    count: process
        wait until rising_edge(clk) and pulse = '1';
        cnt <= cnt +1;
        report "pulse detected";
    end process;

    clk <= not clk after CLK_PERIOD / 2;

    end bench;

enter image description here

I don't understand why the second pulse is printed in gtkwave, while not detected by statement wait until rising_edge(clk) and pulse = '1'

  • \$\begingroup\$ What does "not working" mean? It looks like you want that line to give a single pulse and then silence. What are you actually seeing? If you wanted repetitive pulses, you wouldn't use the infinitely long wait at the end of the process. \$\endgroup\$ – Brian Drummond Jun 26 '18 at 11:29
  • \$\begingroup\$ I added screenshot form gtkwave. I'm confused why the second pulse is printed in the waveform, while not detected in testbench wait until rising_edge(clk) and pulse = '1' statement. \$\endgroup\$ – SlawekS Jun 26 '18 at 13:02
  • 1
    \$\begingroup\$ Much clearer question. Notice that the first pulse is detected at its falling edge, and think about what happens on the second pulse in terms of delta cycles, and you will see that this is expected behaviour. (Then try after CLK_PERIOD + 1 fs to check your understanding. \$\endgroup\$ – Brian Drummond Jun 26 '18 at 13:44
  • \$\begingroup\$ Executing a simple assignment statement "...If the after clause of a waveform element is not present, then an implicit “after 0 ns” is assumed." 10.5 Signal assignment statement, 10.5.1 "A signal assignment statement modifies the projected output waveforms contained in the drivers of one or more signals (see 14.7.2), schedules a force for one or more signals, or schedules release of one or more signals (see 14.7.3)." One schedules a signal update, the other is an signal update scheduled for a particular time. \$\endgroup\$ – user8352 Jun 26 '18 at 17:53
  • \$\begingroup\$ So adding +1 fs gives correct result. But I have some doubts about its performance issues. If we introduce smaller time units does it force simulator to use better time resolution? Please also take a loot at marker in gtkwave screenshot. It is aligned to rising edge of clock and shows pulse is 1. Is it expected behavior too? \$\endgroup\$ – SlawekS Jun 27 '18 at 11:32

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