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Can we say anything about the program counter by looking at the size of a memory chip?

I think the program counter is part of the microprocessor and memory is external. How can we comment about the program counter by looking at the size of the memory?

For example, I had a question in one of my tests:

A memory chip of 8kB has a data bus of 4 bits. What will be the size of the program counter?

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    \$\begingroup\$ The correct answer is "this question is poorly written." In reality, your professor has sme unwritten assumptions in his mind. You are expected to have absorbed his assumptions, and arrive at the answer he expects. It is a crappy way for things to be, but it is often that way. The question ought to be more along the lines of "How large (minimum number of bits) does the program counter need to address program code in an 8kB memory if the memory data bus is 4 bits wide." I'm pretty sure it isn't just that the data bus is 4 bits, but that the memory is organized in nibbles instead of bytes. \$\endgroup\$ – JRE Jun 26 '18 at 11:31
  • \$\begingroup\$ On Harvard architectures, the PC only need to care about program memory size, not address or data bus sizes. Also, CPUs with a MMU might use virtual memory setups that allow the PC to be restricted to a certain size, not necessarily related to the physical memory size. So I don't think you can ask this question about a "general computer". \$\endgroup\$ – Lundin Jun 26 '18 at 11:52
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    \$\begingroup\$ Even if we reinterpret "program counter" to mean "address bus", it is a bad question. Given that the data bus is 4 bits, then one wonders what "8kB" even means. Is is 8192 bytes, addressed in 16384 4-bit words? Or is it 8192 bits (in which case it should have been "8 kb" rather than "8 kB")? Or 8192 words of 4 bits each? \$\endgroup\$ – Henning Makholm Jun 26 '18 at 14:55
  • \$\begingroup\$ Assuming that kB means kilobytes, not kilobits (kb), for an 8kB memory, you need an address bus of at least 13 bits to address every location in memory, independent of the size of the data bus. So you could say that the program counter is at least 13 bits wide. \$\endgroup\$ – DaveBoltman Jun 27 '18 at 8:55
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You can't really make assumptions about the program counter (PC) width from the memory address width.

There have been many many different memory architectures historically, and new ones will undoubtedly be dreamed up. At a very basic level for the simplest of machine, the PC contains the memory address during instruction fetches, so is the same width as that address. However, there are many tricks, even in early machines, that make this more complicated.

For example, machines with virtual memory can logically address more memory than physically exists. The PC would then be wider than the address bus. On a more modern processor operating in "32 bit" mode, the PC would be 32 bits wide. However, that means the PC can only address 4 GB of memory. Many modern machines can address more physical memory than that.

There are a variety of segmentation schemes. The PC is more limited, and some other register holds the upper address bits of the segment the PC is operating in. Jumps within the same segment work normally by loading the PC, but moving between segments is more complicated and requires additional instructions and the like. The actual physical memory could be both larger or smaller than the what the PC can address natively.

Then there are Harvard architectures and the like where there isn't just one memory space, or where execution isn't possible from all of memory.

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  • \$\begingroup\$ The size of the PC does not constrain the maximum memory that can be attached to the system, if there's an MMU involved. The PDP-11 34a I cut my teeth on at university in 1980 had a 16 bit PC, but there was a total of 256K of physical memory attached. And contrary to popular belief, certain 32 bit Microsoft operating systems can use more than 4GB of memory. In particular, the place I worked over the turn of the millennium had a Pentium system (known as "workhorse" IIRC) running 32 bit Windows 2000 pro that had 8 GB of memory installed. \$\endgroup\$ – dgnuff Jun 26 '18 at 21:51
  • \$\begingroup\$ @dgnuff the PAE stuff is a bit restrictive though. It certainly makes sense for servers, where you have lots of "small" processes. If you want to use that Windows 2000 for scientific computing, you're still limited to 4GiB in a single process; utilizing the full 8GiB there will require needlessly complicated programming. \$\endgroup\$ – anrieff Jun 26 '18 at 23:37
  • \$\begingroup\$ @anrieff You are 100% correct. As it happens, the job with "workhorse" was developing video drivers. Supporting PAE to get the extra 4 bits of address space was a royal pain. And yes, any process can only address a total maximum of 4GB on 32bit Windows. However there is a use case that does not involve a large number of small processes: Windows, both workstation and server, will use otherwise unused chip memory for disk cache. Workhorse was, among other things, a fairly large server system, so being able to cache a lot of data was definitely beneficial. \$\endgroup\$ – dgnuff Jun 27 '18 at 0:14
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The only safe way to answer a question like this is to state your assumptions, and then state what flows from them.

For instance -

An 8kB memory needs 13 bits to address it bytewise. If the PC addresses bytes, and the entire addressable program memory space is occupied by this 8k memory, then the PC needs to be at least 13 bits wide.

However, maybe the addressable space is larger, or maybe it's nybble addressable, or maybe only in 16 bit words? All would affect the size of the PC.

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The program counter has to be typically large enough to encode all possible code locations, e.g. if you have 8kB of program memory, that's 2¹³ addressable bytes, so if nothing else is specified, I'd expect the program counter be at least 13 bit wide. 16 bit will be typical, although the hardware doesn't actually need to implement the top 3 bits, so you may have a 16-bit program counter register, where writing '1's to the top 3 bits would be a no-op, those writes would be lost.

However, in reality the true answer is "it's complicated". Different architectures have used all sorts of wizardry (8086 segmented memory access comes to mind) and it's hard to give a definite answer.

Also note that just because you have 8kB of memory doesn't mean all of it has to be devoted to code. Most of it could be data. You may want to read about von Neumann vs Harvard architectures.

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