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Looking at the datasheet for the LM1117 regulator, on page 18 to 20 there's a table of various layouts for copper cooling planes for the LM1117 in SOT-223 and TO-252 packages. Comparing figures 30 and 31 to table 2, I see a number of discrepancies:

  1. for layout 6, the one with the lowest thermal resistance, the table gives upper copper area \$1\textrm{in}^2\$, and 0 for bottom. However, the figures show no copper on top, only on the bottom.
  2. layout 2 has top copper area \$0.066\textrm{in}^2\$, 0 on bottom, and has thermal resistance of \$87 ^\circ \textrm{C}/\textrm{W}\$ for the TO-252. Layout 12 has the same pattern repeated on top and bottom, giving a thermal resistance \$89 ^\circ \textrm{C}/\textrm{W}\$. How can the thermal resistance increase when adding more copper to cool?
  3. On page 4, section 6.4., the table Thermal Information gives a junction-to-ambient thermal resistance \$45.1 ^\circ \textrm{C}/\textrm{W}\$, which is smaller than that reported for any of the layouts on pages 18 to 20. While this table doesn't specify for what layout/heatsinking this is, the footnote on the immediately preceding table says "All numbers apply for packages soldered directly into a PCB." Isn't this a contradiction?

So, my question is: am I seriously misreading/misinterpreting/confusing something here, or is the section in the end of the datasheet full of errors? If it's the latter, where can I find more reliable data to make sure I have enough cooling for my regulator?

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  • \$\begingroup\$ There are plenty of app notes and data based on packages (you might have to pay some attention to whether the lead frames are copper or steel) but the info is pretty spotty. I would suggest making your own measurements if you're running close to the line (or better yet, not doing that in the first place). \$\endgroup\$ – Spehro Pefhany Jun 27 '18 at 14:38
  • \$\begingroup\$ @SpehroPefhany I'm actually trying to figure out if I am close to the line: the current prototype of the device has an LM1117 in a TO-220 package, with no heatsinking, and it rises to 30C above ambient. For mechanical reasons, I need to to switch that to a TO-252 (or smaller SMD). After reading the datasheet and the app notes, I'm a bit lost as to how much, even in order of magnitude, heat sinking copper area I need to add to keep this from being too close to the line... \$\endgroup\$ – Timo Jun 28 '18 at 8:14
  • \$\begingroup\$ Be aware of the per-square thermal resistance of copper foil. For any size of square: 1mm, 0.5mm, 0.2mm, 2mm, 3mm, 10mm, etc. For one ounce/foot^2 copper (the default), Rthermal is 70 degree Centigrade per watt (flowing edge to edge) per square. \$\endgroup\$ – analogsystemsrf Jun 29 '18 at 4:02
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So, my question is: am I seriously misreading/misinterpreting/confusing something

It is a very confusing datasheet. The following is my interpretation.

for layout 6, the one with the lowest thermal resistance, the table gives upper copper area 1in2, and 0 for bottom. However, the figures show no copper on top, only on the bottom.

The patterns are confusing. The bottom view is of the component side, top view is of the opposite side.


How can the thermal resistance increase when adding more copper to cool?

There is copper on the component side and none on the opposite side. All patterns show copper on the component side even if it is not exposed (zero).


On page 4, section 6.4., the table Thermal Information gives a junction-to-ambient thermal resistance 45.1°C/W, which is smaller than that reported for any of the layouts on pages 18 to 20.

45.1°C/W is a different metric. It's the resistance for the package only. In their App Note they say:

The junction-to-ambient thermal resistance, RθJA , is the most commonly reported thermal metric and is the most often misused. RθJA is a measure of the thermal performance of an IC package mounted on a specific test coupon. The intent of RθJA is to give a metric by which the relative thermal performance of a package can be compared.

Source: Semiconductor and IC Package Thermal Metrics

When the package is soldered to the board the thermal resistance of the thermal pad, FR4, and copper is added the package resistance.

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I would take the lack of copper on the drawing for figure 6 as just being an error.

For layout 2 vs 12 there are two possibilities

  • One is that measuring high thermal resistances is a bit of a pain and great accuracy is not to be expected.

  • Copper is rather reflective in the far IR (and by reciprocity can be expected to have low emissivity), if they were running the thing hot enough to have significant cooling by radiation (Goes as the 4th power of absolute temperature) then it is quite likely that the bare FR4 is actually better then bare copper.

Junction to ambient often really means junction to heat transfer tab or pad (In other words, junction to infinite heatsink), you can probably confirm this from the derating curve and the junction temperature limit.

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  • \$\begingroup\$ Texas Instruments pretty much ignores emissivity and radiation cooling according to their app note. They say the purpose of the copper area is a heat spreader. They say solder mask is so thin it is not relevant and the surface material does not matter, only the amount of surface area is relevant. It's been awhile since I read this app note but this is my source for my comment. I found it to be a very worthwhile read: App Note-2020 Thermal Design By Insight, Not Hindsight. ti.com/lit/an/snva419c/snva419c.pdf \$\endgroup\$ – Misunderstood Jun 27 '18 at 18:13

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