PMOS switching circuit

A SPST switch connects HB1 and HB2, to control a lamp connected to HB OUT. I am looking into modifying this circuit to make the slew rate adjustable when switching the output to VCC (around 12V). I would like to be able to control the slew rate with a controller such as Arduino or Rasperry Pi.

The slew rate seems to be affected largely by C1. I found some digitally controlled pots like this one: https://www.sparkfun.com/products/10613 , but there don't seem to be digitally controlled capacitors.

I have also been looking into adding circuitry such as this op amp design from TI to control the slew rate: http://www.ti.com/tool/TIPD140#0

I am a beginner when it comes to electronics so any suggestions/insight would be greatly apprecitated.

  • \$\begingroup\$ Gives me 2 reasons why and values for acceptance criteria \$\endgroup\$ Jun 27, 2018 at 17:49
  • 1
    \$\begingroup\$ What kind of lamp? What kind of "slew rate"? You probably should be using PWM. Running the MOSFET linear is hard on it. \$\endgroup\$ Jun 27, 2018 at 18:15
  • \$\begingroup\$ Is this to reduce current spike or what \$\endgroup\$ Jun 27, 2018 at 18:28
  • \$\begingroup\$ Hi Tony, I want to slow down the slew rate to make it easier on the eyes when the lamp turns on. I'm mostly worried about the off-on slew rate of the voltage at HB OUT. What kind of values are you looking for here? \$\endgroup\$ Jun 27, 2018 at 19:07

2 Answers 2


The conduction of the MOSFET is controlled by its total gate charge \$Q_g\$: operating a MOSFET is equivalent to charging and discharging its gate capacitance, bringing it from its "OFF" state (zero conduction between the drain and source electrodes and \$Q_g=0\$) to its "ON" state (full conduction between gate and source electrodes and \$Q_g=Q_{g\max}\$) and the other way around. The process is exactly the charging of a (nonlinear) capacitor: if you want to control the "speed" of the transition between these conduction states, the simpler way is to control the charging current. Looking at your circuit, the best way is perhaps to change you input saturated switch \$\mathrm{Q}_2\$ with a properly controlled "amplifying" current mirror: the current charging the gate is controlled by the potentiometer \$\mathrm{PT}_1\$, which can be a digital one.


simulate this circuit – Schematic created using CircuitLab


  • By using this circuit, you can control the charging speed of the gate of \$\mathrm{Q}_1\$ without varying its gate capacitance (i.e. without changing \$C_1\$). Lowering the value of \$\mathrm{PT}_1\$ rises the \$I_{C2}\$ current which in turn rises the \$I_{C3}\$ current (the amplifying factor is a function of the values of \$\mathrm{R_{E1}}\$ and \$\mathrm{R_{E2}})\$ and lowers the charging time of the gate of \$\mathrm{Q}_1\$, lowering the rise time of its output. On the other way around, rising the value of \$\mathrm{PT}_1\$ lower the output rise time.
  • Of course you can design a better current controlled gate charging circuit than the one I proposed, but the latter one can be designed to be very fast, if needed.

New edit

A relationship between the input current \$I_{in}\$ from the \$\mathrm{HB}_1\$ switch and the \$I_{C3}\$ discharge current as a function of the resistors \$R_{E1}\$ and \$R_{E2}\$ which can be deduced from the circuit properties of the bipolar junction transistor is the following one: $$ I_{C2}\approx\frac{h_{FE}}{(h_{FE}+1)\frac{R_{E2}}{R_{E3}}+1}I_{in} $$ where

  • \$h_{FE}\$ is the current gain of \$\mathrm{Q}_2\$ and \$\mathrm{Q}_3\$ (assumed to be the same).
  • \$I_{in}=\frac{V_{in}-V_{BE1}}{R_{E2}+R_{E3}}\approx\frac{V_{in}}{R_{E2}+R_{E3}}\$
  • \$\begingroup\$ You are welcome. If you like it, please also consider accepting it. \$\endgroup\$ Jun 28, 2018 at 12:42
  • \$\begingroup\$ Hi Daniele, how should I go about choosing values for RE2 and RE3? \$\endgroup\$ Jun 28, 2018 at 14:18
  • \$\begingroup\$ Peter, I’ll be able to write something about it only this evening, since I am working now. However, the circuit is a variant of the Widlar current mirror: if you know how to design that circuit and you cannot wait until tomorrow, you can try to work out a solution. \$\endgroup\$ Jun 28, 2018 at 14:37
  • \$\begingroup\$ Hi Daniele, okay I'm familiar with the Widlar circuit, I'll see if I get somewhere with that. Thanks again for your help. \$\endgroup\$ Jun 28, 2018 at 15:06
  • \$\begingroup\$ Peter, I had no time yesterday: however in the afternoon I’ll edit adding a solution to the problem. Tomorrow I’ll try write down a full one. \$\endgroup\$ Jun 29, 2018 at 8:35

I don't thnik that HB1 is used for switching issues, since the voltage at HB1 is at vcc unless the fuse F1 melts! Hence HB1 is an input port to detect if the fuse is gone.

The HB2 is used for turning on and off the p-MOS Transistor Q1 via Q2. The positive slew rate can be adjusted by R3 and C3, while the negative slew rate during power-off is adjusted by R1 and C1. But if you are using a controller be sure that the ports can deliver the current!

This circuit configuration also guarantees that the switch is safely off while powering up, which is in most applications a must have!

BTW: I don't think it is clever to use the Q2 as an npn, better use an NMOS instead.


Slew rates in switches are not the same issue as slew rates in op-amps.

In your design you should add an input resistor in series to HB1 for security reason!

  • \$\begingroup\$ Hi abu_bua, thanks for your response. Why do you think its better to use an NMOS? \$\endgroup\$ Jun 27, 2018 at 18:31
  • \$\begingroup\$ Because you can draw the gate to vss, while with a bjt you always have a saturation voltage of ~200mV. That means that Ron will be a little better. Secondly it is easier to make symtetric slew rates. \$\endgroup\$
    – abu_bua
    Jun 27, 2018 at 18:42
  • \$\begingroup\$ This circuit uses high-side switching, so making Q1 an NMOS or NPN transistor is a really bad idea. You will end up with a source follower and the voltage on HB_OUT will never rise above \$VCC-V_{THN}\$. \$\endgroup\$ Jun 27, 2018 at 19:17
  • \$\begingroup\$ @Elliot: Q1 is a npn transitor! \$\endgroup\$
    – abu_bua
    Jun 27, 2018 at 19:23
  • \$\begingroup\$ Are we looking at the same schematic? Q1 has terminals marked G, S, and D. Q1 has the symbol for an enhancement-mode MOS transistor. Your second sentence says "the p-MOS Transistor Q1". Q1 is most certainly not an NPN transistor. \$\endgroup\$ Jun 27, 2018 at 19:55

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