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The following circuit is an active current to voltage converter with switchable gain.

Schematic

Op-amp current to voltage converter with gain switch

Not shown: The inverting input is held low through a 10K resistor when the circuit is powered on but not being used. Whenever a measurement is being made (including calibration measurements where IN is floating), that resistor is disconnected.

Supplies on the analog switches and opamp are +/- 11.5 V. The typical VOUT range is between -10V and +10V.

Purpose

The circuit is used to measure currents in the nanoamp range. A few mV on the output is significant. Constant offsets are not really a problem, as they can easily be calibrated out by measuring the output with an open input and subtracting that from subsequent measurements.

Each board has 6 or more of these circuits.

Components

The selected op amp has very small (< 10 pA) offset and bias input currents and a very small offset voltage (< 1 mV). It's an AD8625AR.

SW1A and SW1B are different poles of the same CMOS switch (ADG1236). They are switched together to select the feedback resistor, which determines the gain of the converter. The maximum leakage current is 1 nA on source and drain pins, on or off. The switch not shown (for holding the inverting input low through a 10K resistor) has similar performance. Typical leakage currents are very small (< 0.1nA).

Problem

The problem I am having is that in some batches of boards, some (or all) of these circuits have large offsets which decay slowly when powered on. However, most boards are perfectly stable at all times, with small offsets.

A typical offset on VOUT with IN floating is < 1 mV. On afflicted boards, the offset can be as high as 120 mV.

When the afflicted boards are powered on, the offset will slowly (after hours of days) stabilize to ~5 mV. After power is removed, the offset accumulates again, so when powering it on after a couple days of being off, it's high again.

Each board has a bunch of these circuits on it. In the first batch of 5 boards, all of them were affected. In the next batch, none were affected. In the most recent batch, each board has one affected circuits, and it isn't always the same one.

At the worst case, the maximum leakage currents of all the analog switches would be 1.2nA, resulting in a 12 mV offset at the highest gain setting, so I don't think that can account for all the offset I'm seeing.

Where else could the offset voltage be coming from? Is there a common board defect that would result in this sort of behavior?

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  • \$\begingroup\$ which opamp are you using? \$\endgroup\$ – markrages Aug 17 '12 at 21:58
  • \$\begingroup\$ It's an AD8625AR. The other channels are being used for other purposes (output buffer for this circuit, and some other stuff) \$\endgroup\$ – Steven T. Snyder Aug 17 '12 at 22:22
  • \$\begingroup\$ What type of capacitors are you using? My immediate thought was "weird capacitor effect"...Rocket Surgeon's answer gives one possibility if you are using plastic film capacitors. If you are using ceramics, another effect is piezoelectricity due to residual stress on the capacitor from the soldering process. But I'm no expert on this and I don't know if 100 mV from this effect is reasonable or not. \$\endgroup\$ – The Photon Aug 17 '12 at 23:43
  • \$\begingroup\$ Is your PCB clean of all flux residues? What construction are C1 and C2? A photograph of the relevant part of the circuit board might give clues. \$\endgroup\$ – markrages Aug 18 '12 at 3:32
  • \$\begingroup\$ @markrages, C1 and C2 are ceramic caps. We had problems with PCBs having flux residue in our first batch of prototypes. It resulted in a measurable leakage current that varied while sweeping a controlled voltage. The vendor acknowledge the problem and addressed it. I inspected these boards with natural light as well as 365nM UV in a semi-dark rom, and there is no visible flux residue. \$\endgroup\$ – Steven T. Snyder Aug 20 '12 at 19:01
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Couple of theories here:

  • How sure are your power supplies are coming up symmetrically?
    If one rail comes up before the other, you may have non-zero output voltages from the op-amp for a very short period of time.
  • Have you implemented all the PCB-layout practices needed for such high-impedances? At minimum, you're going to need guard-rings on all the ultra-high-impedance nodes.
    The National (Now TI) LMC6082 datasheet has a good discussion of what is required to get board-leakage currents low enough to not be a problem.

This will likely not address the possibility that you have dielectric soakage issues, as discussed in @RocketSurgeon's answer.
A good and easy way to test his answer would be to desolder one of the caps on a bad board, and reverse it. If the offset is flipped in the other direction, it's a dielectric soakage issue (because the persistant charge in the cap will have a single polarity). If the offset voltage does not change, the problem is not the capacitor.

One thing I don't see the dielectric soakage issue explaining is why the charge seems to come back when the circuit is unpowered, and go away when it is powered. Since the element that discharges the capacitor is connected continuously across the cap, (e.g C1||R2, C2||R1), the contribution of any current leaking out of the cap should be a constant, and not affected by the supply voltage.

The only thing that comes to mind for me would be that there is something hygroscopic somewhere, and it injects an offset current. When you power the board, it warms up, and drives the moisture out over time. Turn the board off, and it begins to resorb moisture.


One comment I do have is I don't see why you have both SW1A, and SW1B. You can entirely dispose of SW1B. Just tie both of the R/C pairs together, and to the output of the op-amp. When one of the cap/resistor sets is selected, the other will just slowly discharge. As long as one end is floating (which is accomplished by SW1A), the voltage on the other end is irrelevant.

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  • \$\begingroup\$ RE: The power supplies, I'm not sure that they are. Would monitoring the rail voltages at the opamp with a 'scope during power-on be the best way to measure this? \$\endgroup\$ – Steven T. Snyder Aug 20 '12 at 18:04
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    \$\begingroup\$ RE: Layout; there are large clearances (1mm) for the high-impedance nets, but no guard rings. Worst case leakage would be from the 12V rail into this circuit, and requires a 10^9ohm resistance to exceed 1 nA. The only variable voltage near the circuit is the input to the control section of a related circuit. I test leakage from that by performing a full-range voltage sweep while monitoring the output of this IE converter. We previously measured leakage where flux remained on the board, and the test caught it. Here, the offset doesn't vary during the control voltage sweep, only over time. \$\endgroup\$ – Steven T. Snyder Aug 20 '12 at 18:27
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    \$\begingroup\$ RE: Moisture; Good idea! I'll put a board in one of our desiccators for a day or two and see if anything changes. \$\endgroup\$ – Steven T. Snyder Aug 20 '12 at 18:27
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    \$\begingroup\$ @Series8217 - Flux is hygroscopic! That may be the possible moisture-sensitive component. \$\endgroup\$ – Connor Wolf Aug 20 '12 at 23:17
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Theory 1. Soakage. This is dielectric absorbtion effect. AKA soakage. The source of energy is a capacitors charge carried from capacitor's manufacturer testing setup. The film capacitors have been tested by high voltage for few minutes at the factory, then dicharged and stored with open leads.

Over few month the residual absorbed energy (not necessarily the charge, but can be mechanical aging/drying/settling as well) drifts from inside of dielectric layers to the plates. The speed can be very slow, say time constant of polypropilene multiply by thousand (few years for full discharge).

This effect is poorly studied. It affects only extreme circuits like yours with plastic caps and TeraOhm opamps. The best report of effect is done by Bob Pease of Nat Semi when he worked with teflon and pA currents.

The cure for this can be temporary exposure of unpowered circuit to moderate intensity Gamma radiation source for few hours to dissipate all absorbed charges with no physical contact to parts.

Another method, is bying "Older" capacitors, which were stored for few months longer. Compare the dates of caps from good vs bad batch. I bet the older capacitors batch is better.

Or, when ordering caps, ask for those which were stored closer to open window over summer time. Or put assembled unpowered boards onto dry conductive antistatic mat and heat to 150C for an hour (unless cleanliness of pA circuit prohibits any manipulations like this).

Theory 2. Thermocoupling induced current. The thremocoupling current can be caused by difference in temperature across junction of two different metals. To find if it is it, submerse the board into stirred oil bath and compare performance with one in free air.

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  • \$\begingroup\$ The discharge element in this circuit is permanently wired in parallel with the capacitors. As such, I don't see how whether the circuit is powered on would cause the offset to gradually go away, and powering it off would cause it to gradually come back. If there was some leakage out of the cap dielectric, I would expect it to produce a constant (admittedly slowly decaying) offset. \$\endgroup\$ – Connor Wolf Aug 18 '12 at 4:26
  • \$\begingroup\$ Unfortunately, I don't have access to a stirred oil bath big enough for the board. It's 200mm x 280mm. Any recommendations on an alternate method to test for such thermal effects? \$\endgroup\$ – Steven T. Snyder Aug 20 '12 at 21:21
  • \$\begingroup\$ Bob Pease once described the thermal chamber setup with cardboard box and air fan. It may be as good as oil bath if air temperature is stable over long time and fan is stirring the air inside the box. \$\endgroup\$ – user924 Aug 21 '12 at 22:50

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