SPI internals _ missing MISO clock during read operation

Question

I am currently writing C++ code to utilize SPI protocol. I am using popular library as a guide. Run into few questionable areas and after some discussion on the library board forum I have been told "it is an internal problem " ( of the hardware ). To be specific - using MOSI "port" I can "write" to hardware and monitor the outcome via software. Neither MOSI or CLK ports are connected to any SPI slave device. I have no issues there. When I "read" MISO port,again not connected to slave device , I do expect no valid data - no actual MISO signal. That is fine.

However

The master DOES NOT send CLK at all! The master / device empties buffer(s) which are filled DURING the "write" cycles DURING "read" from slave operation.

My actual general question I would like to get answered is

Does SPI master require physical connection to slave to send CLK to slave during slave read operations ?

Per SPI documentation - master sends CLK during "write" to slave and sends CLK during "read" from salve. Master SPI is the CLK source. Only the SPI "write" part works as expected.

Answer 1

Your reference to SPI documentation already provides an answer. Yes, SCLK line is essential for communication, both to and from slave device.

I strongly advise to read that documentation again, it seems you did not understand how SPI works. To begin with, you cannot refer to individual MOSI/MISO/SCLK as "ports". They are communication lines that together form SPI bus, connected to SPI port. While in some cases MISO can be excluded, and SC can be permanently connected you do need at least MOSI and SCLK for sending commands to slave.

Answer 2

In SPI there a master and slave, multiple slaves can be connected to a master. The master supplies the clock, the CS line selects which slave (or if there is one slave activates it for communication). The SCK line is driven by only the master.

The first thing to do in SPI is establish communciation and one of the best ways to do that is to read a register from a spi device (if it has one, some can be write only such as a DAC). If you can't read or write, then verify the timing in the datasheets. The second thing to do is get a logic analyzer and verify the actual signals (otherwise it will not be known if you are commanding anything at all), you also need to verify the voltages and make sure they appropriate. Verify the power of both IC's also.

Answer 3

Here is the thing about SPI: as far as the hardware is concerned, there is no difference between read and write. For each clock cycle, one bit is transferred from the master to the slave on MOSI and one bit is also transferred from the slave to the master on MISO. It’s up to the master and slave software/firmware to determine which bit (or both) is significant.

I can’t talk to your specific master hardware and library but most SPI modules on microcontroller require writing out bytes in order to cycle the clock line. Reading data from the slave is a side effect of writing.

For example, to write one byte to the slave followed by reading one byte back, you would feed two bytes to the transmitter, one data byte followed by a dummy byte. At the same time, you would poll (or use interrupts) for data from the receiver and read two bytes, one dummy which would be discarded followed by the data byte.

Again, I don’t know how your library works but it may require making a write call for enough byte for both reading and writing and then making a read call for the same number of bytes. You would have to write any output bytes followed by enough dummy bytes for the read data. Looking at the received data, you’d need to discard the bytes corresponding to the transmitted data to get at the actual receive data.

Answer 4

There is no difference between a read and write, they come in pairs.
Both cases require the shift register to be clocked out and in.

The only difference is whether a device is a master or slave, which determines where the SCLK comes from, and if CS (chip select) is functional.

You could short MOSI to MISO and have a loopback test mode.