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Is it possible to evaluate the "execution" time of an FPGA design?

I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs.

But now with FF-latches there is a timing constraint, isn't it? I mean, for example if you have the following design :

schematic

simulate this circuit – Schematic created using CircuitLab

If the input changes, it will takes 3 clock cycles for the output to be updated ?

Knowing that, I have a more complex design in Vivado where I can't count the FF-latches in order to determine the "longest" path. But is there an option or a way to do it ?

Bonus question : does a look-up table operation take one clock cycle to be completed ?

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    \$\begingroup\$ no, if you only have combinatorial gates, these still have setup and propagation times: nothing in this world is instantaneous. And in FPGA practice, the time a FF takes to latch a value is typically orders of magnitude smaller than the things you do combinatorially in between flip flops, so you've got everything the wrong way around \$\endgroup\$ – Marcus Müller Jun 28 '18 at 9:03
  • \$\begingroup\$ Oh ok so I was wrong all along... Thank you for enlightening me on that topic by the way ! Actually that does not really change my original question that was to know if it is possible to find the longest path in order to determine the "delay" that there is between the input and the output ! \$\endgroup\$ – Cedric Jun 28 '18 at 9:17
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    \$\begingroup\$ well, yes, any FPGA synthesis tool does that. \$\endgroup\$ – Marcus Müller Jun 28 '18 at 9:22
  • \$\begingroup\$ Ok thank you very much ! I will look for futher information in Vivado documentation. \$\endgroup\$ – Cedric Jun 28 '18 at 9:28
  • \$\begingroup\$ have you got a simulator? \$\endgroup\$ – Jasen Jun 28 '18 at 9:39
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You will need to run a functional simulation to determine signal latency. A complex design can have many paths from inputs to outputs and there is no way for the timing analysis tools to know which particular path is of interest to you. Write a testbench, wiggle the inputs, and count the clock cycles until the outputs change.

Whether a LUT operation takes one clock cycle depends on the delay through the LUT and your chosen clock frequency. That sounds like a silly answer, but the question is poorly framed. An FPGA cannot do anything interesting if you run the clock so fast that a signal can't propagate through a single LUT, so every useful FPGA design has a clock period that is (much) longer than the delay through a single LUT.

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  • \$\begingroup\$ Thank you for the advice ! Actually I checked my testbench and something was missing ! Now I can observe really well the latency of my design. Thank you also for the second part of the answer. \$\endgroup\$ – Cedric Jun 28 '18 at 12:18

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