Is it possible to evaluate the "execution" time of an FPGA design?
I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs.
But now with FF-latches there is a timing constraint, isn't it? I mean, for example if you have the following design :
If the input changes, it will takes 3 clock cycles for the output to be updated ?
Knowing that, I have a more complex design in Vivado where I can't count the FF-latches in order to determine the "longest" path. But is there an option or a way to do it ?
Bonus question : does a look-up table operation take one clock cycle to be completed ?