Is it possible to estimate the execution time of an FPGA design?

Question

Is it possible to evaluate the "execution" time of an FPGA design?

I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs.

But now with FF-latches there is a timing constraint, isn't it? I mean, for example if you have the following design :

^{simulate this circuit – Schematic created using CircuitLab}

If the input changes, it will takes 3 clock cycles for the output to be updated ?

Knowing that, I have a more complex design in Vivado where I can't count the FF-latches in order to determine the "longest" path. But is there an option or a way to do it ?

Bonus question : does a look-up table operation take one clock cycle to be completed ?

Answer 1

You will need to run a functional simulation to determine signal latency. A complex design can have many paths from inputs to outputs and there is no way for the timing analysis tools to know which particular path is of interest to you. Write a testbench, wiggle the inputs, and count the clock cycles until the outputs change.

Whether a LUT operation takes one clock cycle depends on the delay through the LUT and your chosen clock frequency. That sounds like a silly answer, but the question is poorly framed. An FPGA cannot do anything interesting if you run the clock so fast that a signal can't propagate through a single LUT, so every useful FPGA design has a clock period that is (much) longer than the delay through a single LUT.