# VHDL Xilinx IP Core Divisor problem for signed fixed point

I hope you can help me since I believe this is a very specific error and I do not know how to solve.

I want to divide 2 numbers represented like:

• 4bits : integer part
• 4bits : fractionary part

So I instance a divisor in the xilinx core generator and this parameters

• Signed
• Fractionary Part (instead or remainder)

and with this ports:

component div8_signed
port(
clk : in std_logic;
dividend : in std_logic_vector(7 downto 0);
divisor : in std_logic_vector(7 downto 0);
quotient : out std_logic_vector(7 downto 0);
fractional : out std_logic_vector(7 downto 0)
);
end component;


Then for testing I try to implement the division between these numbers (for example):

• Division1: - 2 / 1.5
• Division2: - 1.5 / 2

So I do fixed point calculations before going to the VHDL and I get these values with this representation:

Division 1:
r = x/y
Floating P. Fixed point  Hex  Bin
x: -2.000000, X: -2.000000 0xe0 0b11100000
y: 1.500000,  Y: 1.500000  0x18 0b00011000
r: -1.333333, R: -1.312500 0xeb 0b11101011

Division2:
r = x/Y
Floating P. Fixed Point  Hex  Bin
x: -1.500000, X: -1.500000 0xe8 0b11101000
y: 2.000000,  Y: 2.000000  0x20 0b00100000
r: -0.750000, R: -0.750000 0xf4 0b11110100


So I get it simulated and here are the results:

The quotient and the fractionary part are wrong according to my calculations. I know that I would need to take the last 4 bits of the quotient for the integer part of the result and the first 4 bits of the fractionary for the fractionary part. But still the quotient and the fractionary shows numbers that do not match with what I was expecting to see.

Doing some trial and error I found that for divisions of signed numbers in the next combinations work or not:

• positive / positive : works
• negative / negative : works
• positive / negative : do not work
• negative / positive : do not work

I have already tried everything without success and I do not know how to make this work. Any idea of what can be happening?