# verilog assign memory in a memory

I want to assign a memory 64x6 in a memory 64x6 by saying that all the 64 rows in memory_2 will be equal to all the 64 rows in memory_1, how to make that in verilog ?? knowing that it is very easy in MATLAB as it is matrix based

• Algorithms are applicable to every type of industry out there. It's almost like a plan for attack. Think about how you would do it on circuit diagram and then try to translate it over. That's where you can define your devices and connections, etc. for Verliog. – KingDuken Jun 29 '18 at 14:15
• Do you want to copy one memory to another during operation, or do you just want the initial state of the system to have the same data in both memories? – The Photon Jun 29 '18 at 15:13
• @The Photon no copy one memory to the other but in only one cycle – Aren dg Jun 29 '18 at 18:17
• @Arendg, does it need to be synthesizable? Because real memories don't work that way. – The Photon Jun 29 '18 at 18:23
• Well, you could I suppose implement both memories in fabric as a couple of huge banks of D types, then a parallel copy would be maybe possible, but the thing would be huge and slow. – Dan Mills Jun 29 '18 at 18:41

Build a state machine to do the copying by routing the data output of one memory to the data in of the other, counting up addresses and manipulating the strobes appropriately?

You are probably going to want a mux or two to switch the bus routing appropriately.

HDLs are hardware description not software, think in terms of what circuitry you would need, the answer generally drops out from that question.

You could output Verilog from Matlab... (and, cross your fingers and hope it works)

RTL: If concurrent, all you need is a common address, data and control to both memories. If writing 2nd memory after 1st, you need a memory controller to read 1st and write 2nd. You can't just "magically" move data in HW

Behavioral: You should be able to use clone operation (i.e deep copy) You can do this in Systemverilog (IEEE-1800), not Verilog (IEEE-1364) (Usually a simulator license feature you would need). Although, clone may only be available in a class (i.e. OOP-space of IEEE-1800 Standard). In Verilog, you could probably do a for each loop.

You could also put a picoblaze on there and simply do it in software. They take up very little space in hardware, and they are free as in beer to use. Also quite well documented, you can get up and running with this soft processor in a few hours. This might be a good fit for your design, particularly if there are other functions that it could perform.