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Is Fermi level of p or n type semiconductor constant with respect to applied voltage ? Please explain. From the attached image it seems Fermi level of intrinsic semiconductor varies but that of extrinsic semiconductor is constant.enter image description here

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Fermi level is defined only in equilibrium. Not when bias is applied. In that case there are only quasi-fermi levels, usually marked with \$E_{Fn}\$ and \$E_{Fp}\$. The current through the device will be proportional to the gradient of quasi-fermi levels. So if no current flows, then the quasi-fermi levels will be flat. The band diagram shown in figure represents a MOS capacitor and no stead-state current can flow through an ideal MOS capacitor and hence the quasi fermi level is marked flat.

Intrinsic fermi level (\$E_i\$) is the fermi level of an intrinsic semiconductor at equilibrium. This level is fixed with respect to conduction and valance band. So if band edges change (with position), \$E_i\$ also changes.

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Fermi-level of any semiconductor depends only on two factors:

  1. Doping
  2. Temperature

In equilibrium the distance of fermi level from conduction band and valance band is fixed. Now if you apply battery, the bending of the bands will be such that the distance of fermi level from Ec and Ev remains same. In the given MOS capacitor, the semiconductor is at negative potential of battery (Inversion), hence raising the band level against the oxide surface. Which causes the fermi level of semiconductor to go beyond the metal fermi level (which were initially coinciding). While intrinsic fermi level is shown bend at interface as usual. (fixed with respect to Ec and Ev).

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