# Intel/Altera FPGA bidirectional DQS timing constraint

I have a DDR controller implemented in an FPGA using Altera/Intel/Quartus, and I'm trying to get the constraints correct for the bidirectional DQS pin. This pin is a data strobe pin that the DDR device drives during reads, and that the FPGA drives during write. The data valid windows have setup and hold times relative to this DQS pin, and it changes depending on reads or writes.

During writes, I try to center the data-valid window around the DQS strobe by output-registering the data pins with a 0-degree clock, and output-registering the DQS pin with a 90-degree clock. This gets the data out much sooner than the DQS strobe.

Here's my SDC timing constraint attempt on the input path:

create_clock -name CLK_ddr_ldqs_INPUT -period $DDR_CLK_PERIOD [get_ports ddr_ldqs_n] set_multicycle_path 0 -from virt_clk -to CLK_ddr_ldqs_INPUT set_input_delay -clock virt_clk$tDQSQ -max [get_ports $input_ports] set_input_delay -clock virt_clk -$tQHmin -min [get_ports $input_ports] set_input_delay -clock virt_clk$tDQSQ -max [get_ports $input_ports] -clock_fall -add_delay set_input_delay -clock virt_clk -$tQHmin -min [get_ports $input_ports] -clock_fall -add_delay  And here's my attempt on the output paths: set CLK_ddr_ldqs_n_OUTL CLK_ddr_ldqs_INPUT; set_output_delay -clock$CLK_ddr_ldqs_n_OUTL $tDS -max [get_ports$input_ports]
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL -$tDH -min [get_ports $input_ports] set_output_delay -clock$CLK_ddr_ldqs_n_OUTL $tDS -max [get_ports$input_ports] -clock_fall -add_delay
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL -$tDH -min [get_ports \$input_ports] -clock_fall -add_delay


However, the problem that I am having is that when I view the output paths in the TimeQuest analyzer, it shows that the launch clock is the 0-degree clock, but the latch clock is also a 0-degree clock. The latch clock should be a 90-degree version.

The TimeQuest seems to label the clocks correctly: Launch Clock = pll1|clk[0] (this is the 0-degree clock), and Latch Clock = CLK_ddr_ldqs_INPUT.

I'm pretty sure this is probably just a quirk with how I'm defining the constraints, so I tried a few other examples I've found online, replacing the set CLK_ddr_ldqs_n_OUTL CLK_ddr_ldqs_INPUT; statement with :

create_generated_clock -name CLK_ddr_ldqs_n_OUTL -source { inst5|altpll_component|auto_generated|pll1|clk[3] } [get_ports ddr_ldqs_n]


pll1|clk[3] is the 90-degree version.

But I get a warning saying "ddr_ldqs_n already has a clock associated with it, use the -add flag to reuse the pins", and then the build ends end an error stating "Cannot find clock CLK_ddr_ldqs_n_OUT". I tried doing what it said and putting a "-add" in the command. Doing this removed the warning, but I still get the error.

Can anyone spot the problem in how I'm doing this?