I looked at the following in hopes my question will be answered:
But the answer was vague. It stated:
"though there is a 'strong' source transistor that comes on briefly when the pin is switched from '0' to '1' in order to charge stray capacitance connected to the pin quickly"
This suggests to me that as soon as I set a GPIO pin value to high on my AT89C2051 (assuming the external thing connected to it is high impedance or nothing), there is a delay I need in my code before the pin is officially recognized as high.
I included a basic skeleton of my code below. Basically an "ack" pin follows the clock when operations are complete. If that "ack" pin is forced low externally then a reset bit is forced on. The problem is I don't know how much delay to include in my program.
What I do know is each "nop" takes about 0.54uS to execute because I'm using a 22.1184Mhz crystal on my AT89C2051.
clr 20h ;turn reset off clr P1.1 ;turn ack off setb P1.2 ;allow clock as input only mainloop: main1: acall someasyncfunction clr P1.1 ;ack=current clock state jnb P1.2,main1 ;wait till clock switches netmain2: acall someasyncfunction setb P1.1 ;ack=current clock state ;how many nops??? jb P1.1,notrip ;If user pulls ack low then set reset setb 20h notrip: jb P1.2,netmain2 ;wait till clock switches acall postprocessing sjmp mainloop
My immediate guess to the calculation is to find the biggest capacitance value mentioned in the datasheet and multiply by the resistor connected to the GPIO pin (or if no resistor is connected, then multiply by whatever the internal resistor is?)
I'm also powering the thing with regulated 5VDC.
Anyone know the math to this so I know the minimum number of "nop"s I need to add between when the pin is internally set high and when valid data can be read from it?
And please be more specific than just a 2 * R * C because I need to know the R and C you refer to.