# Calculating required delay before pin value is recognized in 8051

I looked at the following in hopes my question will be answered:

can we use 8051 pin as Input and output at a time?

But the answer was vague. It stated:

"though there is a 'strong' source transistor that comes on briefly when the pin is switched from '0' to '1' in order to charge stray capacitance connected to the pin quickly"

This suggests to me that as soon as I set a GPIO pin value to high on my AT89C2051 (assuming the external thing connected to it is high impedance or nothing), there is a delay I need in my code before the pin is officially recognized as high.

I included a basic skeleton of my code below. Basically an "ack" pin follows the clock when operations are complete. If that "ack" pin is forced low externally then a reset bit is forced on. The problem is I don't know how much delay to include in my program.

What I do know is each "nop" takes about 0.54uS to execute because I'm using a 22.1184Mhz crystal on my AT89C2051.

clr 20h ;turn reset off
clr P1.1 ;turn ack off
setb P1.2 ;allow clock as input only

mainloop:
main1:
acall someasyncfunction
clr P1.1     ;ack=current clock state
jnb P1.2,main1 ;wait till clock switches

netmain2:
acall someasyncfunction
setb P1.1          ;ack=current clock state
;how many nops???
jb P1.1,notrip     ;If user pulls ack low then set reset
setb 20h
notrip:
jb P1.2,netmain2    ;wait till clock switches

acall postprocessing
sjmp mainloop


My immediate guess to the calculation is to find the biggest capacitance value mentioned in the datasheet and multiply by the resistor connected to the GPIO pin (or if no resistor is connected, then multiply by whatever the internal resistor is?)

I'm also powering the thing with regulated 5VDC.

Anyone know the math to this so I know the minimum number of "nop"s I need to add between when the pin is internally set high and when valid data can be read from it?

And please be more specific than just a 2 * R * C because I need to know the R and C you refer to.

The far more productive approach to this, because the R and C values for every board and design are different, is to observe the waveforms on an oscilloscope. You should be able to measure the port pin going high relative to the XTAL2 pin to infer the relationship between the program instruction flow and the pin state change.

It can also be informative to have a program test made up that just toggles the port pin high and low and then compare that to the XTAL2 to see if there is a difference between the two transitions.

If you do not have access to an oscilloscope you should get one. When working in embedded electronics it is an almost essential tool.

Lastly let me comment that the delay needed for your ACK could just be as simple as just trying out one NOP. The internal dynamic pullup FET that improves the output rise time has a fairly low impedance and will charge the external capacitance in the few tens of picofarads very quickly. If I recall correctly the speed up FET is only kept in for one clock cycle (maybe 2).

The strength and duration of the low impedance "pulse" is defined in the datasheets. For a standard 8051 it is 1/6th of the opcode cyle. So you don't need a delay in the very most cases.

However, if your stray capacitance is really high, I'd suggest to add a driver. After the mentioned duration the usual high impedance driver is pulling the pin high. If the low impedance driver didn't get the voltage high, the low impedance driver will need so much more time.

As @MichaelKaras said you should use an oscilloscope to watch what is happening.