I am working on a FPGA project where a host CPU writes a 10,240 x 16-bit look up table into FPGA logic. To implement this, I've utilized on-chip memory to store the values and read them out when ready.
An external trigger/go pulse kicks off a processing cycle which lasts several hundred thousand clock cycles. Once we get this trigger, the state of the 10,240x16 LUT needs to be frozen or latched, so it can be utilized during the processing cycle. Unfortunately, the data needs to be available fairly soon after this "GO" pulse, so there is not enough time to do a complete buffer copy.
The host also needs to be able to continually update some values of the look up table while the current cycle is being executed, in order to setup for the next processing cycle. To allow for both cases (latching the state of the lookup table, but also letting the host update it whenever), I think that double-buffering ping/pong style is the way to go: The host writes to one buffer until we get to "GO" command, then the host writes to the other. The FPGA logic always reads out of the buffer not being written to.
However, since the host is not rewriting all 10,240x16 values when it does its sporadic updates, the buffer that is not being written to is essentially "dropping" the updates while it's frozen.
Is there a novel way to handle this scenario? I'm thinking there needs to be some kind of buffer resynchronization process once the buffer is unfrozen.