I need help understanding a stateflow diagram. I'm supposed to design it in VHDL as a beginner's exercise.

I've gone through the VHDL tutorials on nandland.com, and could say I understand the basics of VHDL.

What I don't understand is what this state diagram means.enter image description here

Could someone help me with that? You don't have to write the code, I just need to know what the diagram means.

Noob question, I know. But I'm new to this.

Thanks in advance.

Edit: Here's where I got the question from. The question says I should replace X with 0. enter image description here

  • \$\begingroup\$ Where did you get the diagram? Unfortunately, state diagram notation is not completely standardized. Also, I think there is a problem with the diagram you have shown, unless there is some explanation that goes along with it. \$\endgroup\$ – Elliot Alderson Jul 2 '18 at 13:33
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    \$\begingroup\$ As far as I can tell, your questions has nothing to do with VHDL but is rather about what exactly a Mealy state machine diagram represents. en.wikipedia.org/wiki/Mealy_machine \$\endgroup\$ – po.pe Jul 2 '18 at 13:36

What you have there is the state diagram of a Mealy Statemachine (en.wikipedia.org/wiki/Mealy_machine)

It's a very simple one that has only 1 input and 1 output, that's what the notation on the transition arrows represents (input/output). I'm wondering where you found this diagram, because it doesn't make much sense. So what this diagram technically illustrates is the following

  • Let's assume the entry point is SA (State-A)
  • If your input is '1', the transition guard to SB is true, so you change to SB and set the output to '0'. At SB (State-B) you have the same transition guard to SC (State-C) and again the output is '0' - so for now this is your final state.

What's rather strange are the two transition guards between SA and SC, both have a guard of input '0', this means from any of the 3 states you'll end up toggling between these two states as long as your input is '0' - as correctly mentioned in the comment, the output would toggle as well.

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    \$\begingroup\$ You'll end up toggling between the states and also toggle your output. It's basically a clock gate. \$\endgroup\$ – DonFusili Jul 2 '18 at 14:39

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