I need help understanding a stateflow diagram. I'm supposed to design it in VHDL as a beginner's exercise.
I've gone through the VHDL tutorials on nandland.com, and could say I understand the basics of VHDL.
Could someone help me with that? You don't have to write the code, I just need to know what the diagram means.
Noob question, I know. But I'm new to this.
Thanks in advance.