0
\$\begingroup\$

I have a BSDL file for a device for which I need to generate test patterns through an FPGA. I learnt that BSDL is a subset of VHDL but the file looks like it describes the hardware of the DUT. I know this file is interpreted by an ATE which I don't have access to for obvious reasons. Is there any tool that can generate synthesizable RTL that can I can put into the FPGA to generate the vectors described by the BSDL file?

\$\endgroup\$
0
\$\begingroup\$

BSDL is Boundary Scan Description Language. It describes, as it says, the boundary scan architecture of a chip/die, i.e. mapping between pins, internal IO pads and boundary scan cells in a way you can drive an internal test or an external test.

From IEEE-1149.1 § B.3:

BSDL is not a general-purpose hardware description language—it is intended solely as a means of describing key aspects of the implementation of this standard within a particular component. A BSDL description is not itself a simulation model.

BSDL is a subset of VHDL in the sense its designers reused entity declaration and attribute statements from VHDL (mostly), and specified another language actually embedded into string literals. To me, this is another language. VHDL reuse is only useful when it comes to custom BS Cell definition that can be embedded in VHDL packages (IEEE-1149.1 B.10), something nearly nobody uses.

For board-level testing, an ATE cannot do anything useful with only BSDL of chips. It also needs the netlist. Alternatively, an ATE may use test vectors that were generated from BSDL and Netlist and saved to a test vector format, like SVF or HSDL.

So, for your initial problem: as there is no real synthesizable information in BSDL, there is no point in converting it to Verilog.

\$\endgroup\$
  • \$\begingroup\$ So you are saying an ATE can not use BSDL alone to generate the test vectors. Actually I do have an hsdl file generated from Mentor tessent tool, but since the syntax looked like VHDL I thought it was BSDL with different file extension. \$\endgroup\$ – Pramod Jul 4 '18 at 17:42
  • \$\begingroup\$ My problem is I need to access this test logic from an FPGA, for which I need loads of RTL, which may easily become as complex as the DUT that I am supposed to test. So if there is already information about the test logic and the test vectors in some format, I want to know if there are any ways to make the job easier. \$\endgroup\$ – Pramod Jul 4 '18 at 17:58
  • \$\begingroup\$ Then I understand you actually have HSDL test vectors, and you want to basically implement an ATE in a FPGA, then ? This is definitely doable. \$\endgroup\$ – Nipo Jul 4 '18 at 18:38
  • \$\begingroup\$ Yes, I have done it manually earlier by studying tool generated test benches, deriving test vectors and writing RTL to replicate same patterns. But now I have to work with large designs so it is impractical to do so. Are there any standard ways or affordable commercial tools that can do this? Thanks for your time.. \$\endgroup\$ – Pramod Jul 4 '18 at 19:01
  • \$\begingroup\$ I have no idea about commercial tools. But you can certainly parse test vectors in a PC and send them through some fast link (ethernet, FTDI, FX3, ...) to a FPGA that does the stimuli and result assertion. You could even to it all-in-one in a SoC like a Zynq. \$\endgroup\$ – Nipo Jul 4 '18 at 19:23

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.