# If constraints in SystemVerilog

I have a class of sequence item with rand variables:

class my_seq_item extends uvm_sequence_item;
rand bit a, b, c, d;


I want to generate a random bit for 'd' only if 'b' and 'c' are 0. How do I write a constraint for this?

• What should bit 'd' be otherwise? Or stay the same? Jul 4, 2018 at 21:07
• bit 'd' should be 0 otherwise. If b and c are 0, bit d should be 1 Jul 4, 2018 at 21:54

constraint my_constraint { if (b==0 && c==0) d==1; else d==0;}