I have a class of sequence item with rand variables:
class my_seq_item extends uvm_sequence_item;
rand bit a, b, c, d;
I want to generate a random bit for 'd' only if 'b' and 'c' are 0. How do I write a constraint for this?
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\$\begingroup\$ What should bit 'd' be otherwise? Or stay the same? \$\endgroup\$ – Oldfart Jul 4 '18 at 21:07
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\$\begingroup\$ bit 'd' should be 0 otherwise. If b and c are 0, bit d should be 1 \$\endgroup\$ – pavan sp Jul 4 '18 at 21:54
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constraint my_constraint { if (b==0 && c==0) d==1; else d==0;}
