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I am designing a SEPIC converter using a LT8364 for "power aplications" and a buck converter using a TPS62125 for powering a MCU.

Since I have a bunch (>100pcs) of 100uF, 16V, electrolitic caps laying around, I would like to use them to store a of bit current at the exit of thesse two switching converters.

I understand that using a big capacitor is better if you have an instant and huge current need, but I do not know what happends when you start everything up.

Question 1: Would a 100uF electrolitic capacitor draw an extremly high current at startup, as all capacitors do when they are being charged up and therefore would it destroy the IC or the inductor or would it be just fine because it's only high current for a fraction of a second?

Question 2: Would it be more effective to use a smaller value ceramic capacitor?

P.S. For the SEPIC, output would never go over 14V.

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    \$\begingroup\$ Capacitors do not store current. \$\endgroup\$ – Olin Lathrop Jul 5 '18 at 18:29
  • \$\begingroup\$ 100uF should not hurt the supply, but go by the example schematics they show. Often switch-mode power supplies use several output capacitors in parallel to get a low ESR, in addition to 100 nF caps. \$\endgroup\$ – Sparky256 Jul 5 '18 at 19:24
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Would a 100uF electrolitic capacitor draw an extremly high current at startup, as all capacitors do when they are being charged up and therefore would it destroy the IC or the inductor or would it be just fine because it's only high current for a fraction of a second?

No the IC would protect itself and, in addition, the LT8364 has a programmable soft-start option: -

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SS: Soft-Start Pin. Connect a capacitor from this pin to GND copper (near FBX) to control the ramp rate of inductor current during converter start-up. SS pin charging current is 2μA. An internal 220Ω MOSFET discharges this pin during shutdown or fault conditions.

For the TPS62125, if you read the data sheet it tells you that there is internal current limiting circuit (max 900 mA) - see page 5 of the data sheet - this is to prevent the inductor going into saturation primarily but serves the purpose you appear to want.

There is also a 200 us output voltage ramp time to reach 1.8 volts and this means that dV/dt = 9 V / ms so, if the capacitor is (say) 100 uF, the current cannot be higher than 0.9 amps (coincidentally as per the current limit circuit).

Generally, you can assume most modern switching controllers will have features that protect themselves against load currents that are too high and these are no exception.

Would it be more effective to use a smaller value ceramic capacitor?

Use what is recommended in the data sheets = usually means use a ceramic for modern devices.

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Instead of guessing, do the math. The current thru a capacitor is:

    I = dV C / t

Where I is the current, dV is the change in voltage, C is the capacitance, and t is the time over which the voltage change occurs. In common units:

    A = V F / s

A is Amps, V Volts, F Farads, and s seconds.

So to answer the question about inrush, you have to know to what voltage the capacitor will be charged to in what time. You haven't given us a schematic and enough specs, so we can't give you any numbers.

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Most integrated converters have soft-start and/or cycle-by-cycle current limit. So in general no, nothing will be destroyed with large output capacitance. (Read the datasheet.)

However, that doesn't mean that the converter will be stable or have good performance. You should check the datasheets for the parts to see how to select the appropriate amount of output capacitance AND then do some testing to see how it performs.

The exception may be the boost converter where inrush flows directly through the inductor and diode or sync FET to the output caps. In that case depending on the component ratings you could conceivably damage components. If not from the inrush sometimes from the converter starting while the inductor is still saturated from the inrush. This is common in PFC boost converters.

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Power supplies must have specifications for ripple and load regulation.

Your primary choices are switching frequency, Inductance and load capacitance.

Your secondary choices are Switch RdsOn, DCR (L) + Imax(L) >2x load max=>> ESR of Cap. This affects ripple voltage and loop stability compensation needed at unity loop gain f.

Then your Rule of Thumb for values should be in the range \$L*C~=~30~ to~ 150~*1/\omega ^2\$.

This follows your datasheet example from Buck to Boost.

Making C bigger also makes Low ESR caps more expensive as the best have ESR* C=1us which is critical when using >1MHz switching rate and often low ESL multiple smaller load caps achieve this.

Then verify your loop RC compensation choice by optimizing step load on/off results 100%~10% for example and adjust as required.

Generally ESR+DCR* RdsOn total < ~=1%V/Imax

But always start with full test acceptance criteria, consistent with good commercial designs. Then use above with datasheet to choose all parameters.

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