# measurement of output impedance of a CMOS inverter

I am measuring output impedance of CMOS inverter using ngspice.

No matter how I measure the output impedance, the result can never come any close to the following theoretical calculation if I reduce the value of Rf. Could anyone help ?

https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.pmos

https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.nmos

ngspice netlist for output impedance measurement

*CMOS inverter

.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6

*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0

*** *** INPUT SIGNAL *** ***
** VSIG IN VSS 0
** VSIG IN VSS AC 1 DC 0
** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'

*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=2U L=2U
MN OUT IN VSS VSS N1 W=1U L=2U

** CL OUT VSS 3p
** RIN IN VSS 1G

CIN IN VSS 1E9
Rf OUT IN 1E9
** Lf OUT IN 1E-12
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292

*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
*** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
IOUT VSS OUT AC 1

*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos

.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6

let ROUT=OUT/abs(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc

.END


ngspice simulation result = 60 kilo ohm

ro_p theoretical calculation for PMOS

ro_n theoretical calculation for NMOS

ro_equiv Output impedance calculation of CMOS inverter = 56 kilo ohm

• Vsig is keeping the input grounded, so one of your transistors is definitely not in saturation. I'd remove it and let Rf take care of it. Also, the total output impedance will be the parallel output impedance of the nmos and pmos. You'll have to keep that in mind when comparing to the model equations. – Sven B Jul 7 '18 at 9:00
• @SvenB VSIG IN VSS AC 1 DC 0 ? If I use this VSIG, then with some network/superposition theory, the AC output impedance result will be superposition between this input voltage VSIG AC source and output node AC current source. What do you think ? – kevin Jul 7 '18 at 10:00
• So, you have the ngspice result at 60k, while the other model gives 56k, and you call it "never come any close"? This is a very odd sense of numbers... – Ale..chenski Jul 7 '18 at 16:56

You should really draw the circuit you're using to simulate this as you need to get the inverter biased at the right operating point by shorting the input to output via a resistor and removing any AC from the input. From the netlist it looks like you've done this correctly.

But then you seem to apply a DC signal at the input of 0 Volt:

VSIG IN VSS 0

That's no good!

I would use this:

simulate this circuit – Schematic created using CircuitLab

Then do an AC analysis over frequency. As Zout = Vout/Itest and Itest = 1 (due to AC magnitude = 1 of Itest) You can just plot the magnitude of V(out) and that will be the output impedance.

• See my updated first post. So, no VSIG at all ? I understand that R1*C1 time constant has to be large to only let the feedback be only at DC. However, could we really make R1 large ? What about voltage drop across R1 ? Besides, modifying R1*C1 time constant makes huge difference in the simulated result. I am not sure if RC self-biasing method is suitable. – kevin Jul 7 '18 at 13:22
• Therefore, I am thinking of using just an inductor instead of R1 and C1. However, using inductor as feedback will only leave the input (gate) of the CMOS inverter dangling. Is this a right thing to do in AC simulation since I am also getting sme weird simulation result using inductor self-biasing method ? – kevin Jul 7 '18 at 13:22
• So, no VSIG at all No voltage no, I use a current, it is Itest, call it ISIG if you like. Using a current instead of a voltage seems scary but it's not. How much DC current will flow through R1? I hope you say "zero", then how much DC voltage will be dropped across R1? Yep, zero as well. The huge value of R1 is ony relevant for the RC time constant. You should choose to read the value of the output impedance at the frequency you're interested in. Ignore anything under 1 Hz. Using an inductor will make things even more complicated and it is of no use. – Bimpelrekkie Jul 7 '18 at 15:19
• When you add an inductor you make it a 2nd order system which can have LC resonances. There's no need to use an inductor. But please prove me wrong if you think you know better :-) I sometimes also used an inductor in my younger days, until I found out RC works just as well and avoids some complications. – Bimpelrekkie Jul 7 '18 at 16:48
• I will end up with 8 kilo ohms lower compared to theoretical calculation Don't say it like that because on 1 M ohm, 8k ohm off is nothing. It is more illustrative to say "It is 10% off". From the graph I read about 60 kohm. If your calculation gave you 68 k ohm you should be happy! That's less than 10% off. If your goal is to make the numbers match within a few % forget it, that's not going to happen. You would have to take all the effects which the simulation model takes into account also into account and that will result in a mess of formulas. – Bimpelrekkie Jul 9 '18 at 14:08