5
\$\begingroup\$

Introduction:

I am designing a hobby electronic for first time, using STM32 to control a soldering tip. I read many documents of PCB layout, and also many information from this forum. And this is my first result, I am going to let this design be manufactured by PCB manufacture.

Since this is my first attempt, I would like to have some advice to check whether I'm doing wrong or not, before I send this design out to the factory.

This PCB will be a double layer PCB.

The components are going to be soldered by hand.

I am designing the PCB with EAGLE education version. (2 layers only)

Crystal Layout:

From this document I learned :

  • To have a GND island in bottom layer and guard ring on top layer to protect the OSC signal.
  • The isolated ground island should be connected to the nearest MCU ground.
  • The guard ring should be stitched by via to the ground island.
  • No signal should run through the isolated ground area.
  • The signal paths of OSC should be symmetrical as possible.
  • The signal paths of OSC should be short as possible.
  • Return paths of load C goes through via to Ground island

My OSC is running in 8 Mhz; load C are 18 pF.

I hope I understood the rule correctly, and also do the layout correct in the range of a hobby board.

Power and Decoupling C:

I am using 0603 cap. I want to keep the ground plane as whole as possible, so I don't want the signal trace go to the bottom layer. But I also can not keep the decoupling C on the top layer. That's why I moved decoupling C to the bottom layer. If any idea can be provided, which can make both traces and decoupling C on the top layer, will be very appreciated.

What I got as rules:

  • The decoupling C should be placed as close as possible to the VDD/VSS pair.
  • Power first go through the decoupling C then to the VDD/VSS pins
  • MCU has local +3V3 and GND. And they are feed from a single point.
  • Keep the ground plan not be cut.
  • For the VDDA, a ferrite bead is needed.
  • If multiple C are needed, place the C with smaller value closer the the VDD/VSS pair.

Please let me know, whether my layout is reasonable.

ADC signal:

for my application a thermocouple signal is needed, which is in the soldering iron tip. The the tip has a heater resistor and a thermocouple inside and the thermocouple and heat resistor are sharing a common return path. The thermocouple voltage is measured in the period, when the heater voltage is not applied.

I am using a very simple non-inverted op amp to amplify the signal. What I am concerning about are:

  • whether the return current of heater element will give big disturbance to the MCU. (Since the thermocouple voltage is only measured when no heater current flows, it doesn't matter that the current is effecting the op amp)
  • Is it better to tie the OP amp VSS to the ground plane directly, or tie it to the thermocouple(-) as I did in the design? Or other options?

Schematic:

I am using a STM32F103C8T6. According to datasheet, .1uF and 2x 10uF for VDD/VSS pair. For fast signal I placed resistor for raising edge suppression. A cap is placed for filtering reset line. I am using SWIO for debugging port with SDO tracing.

Following sections is my current PCB design:

-Schematic:

enter image description here

-TOP:

The dash line is the 3V3 cutout for separating VDD pins and +3V3 plane Top layer MCU close top

-BOTTOM:

The dash line is the GND cutout for separating VSS pins and GND plane Bottom layer MCU close bottom

-Analog part:

op amp

-Soldering Tip construction:

enter image description here

I hope the information I provided is enough to generate some feedback.

And also let me know, whether my understanding of design rules are correct.

Thanks a lot in advance.

Best regards.

\$\endgroup\$
  • \$\begingroup\$ Which STM32 exactly? Do you need precise timing? \$\endgroup\$ – Jan Dorniak Jul 8 '18 at 1:43
  • \$\begingroup\$ Also a schematic would help. \$\endgroup\$ – Jan Dorniak Jul 8 '18 at 1:46
  • \$\begingroup\$ Hi Jan, thanks for your comment. I added schematic of the MCU part in the editing. The MCU is a STM32F103C8T6. I won't say it needs precise timing. But I am wondering, how tight the application will be to be consider as "needing precise timing"? precision of +/- 100 ns? The 800kHz PWM is controlling WS2812B led. the tolerance is +/-150 ns. I tried this design on the bread board and measured with osci. It works. Could the signal be worse on a PCB than on bread board? \$\endgroup\$ – MinShu Huang Jul 8 '18 at 9:41
  • \$\begingroup\$ wrong wording on my part possibly. More along the lines of clock precision - I don't think you need that crystal at all. The HSI oscillator should have something on the order of +/- 3%. Also adding NRST to your programming connector while not strictly necessary is very helpful. \$\endgroup\$ – Jan Dorniak Jul 8 '18 at 16:49
  • 2
    \$\begingroup\$ NRST routing sounds good. As for the crystal - IMHO it looks overdone. I've seen working boards with a 25 MHz crystal which use a single ground for everything, but I'm not a specialist. Also I've been taught to put caps between the crystal and the MCU but that's just knowledge passed down in my office. \$\endgroup\$ – Jan Dorniak Jul 10 '18 at 8:18
0
\$\begingroup\$

Just quickly skimmed over it, but two things are bothering me:

  • What is the dotted line on the top layer around your MCU? It looks like some kind of outline from another layer that somehow ended up on the copper layer. You should remove it or it will cause shorts.
  • On the analog part, the spacing between some traces and (mainly) the ground copper pour seems to be very small. That may cause problems in manufacturing and also cause shorts. There should be a setting in EAGLE to define the minimum distance of nets (traces) to the copper pour.

    I placed yellow circles on the affected areas:

layout with highlighted areas

\$\endgroup\$
  • \$\begingroup\$ The dotted line is a poligon outline showing. It is fixed once Eagle recalculates pours/poligons. \$\endgroup\$ – Jan Dorniak Jul 8 '18 at 1:41
  • \$\begingroup\$ Hi Marco, thanks for your input. The dash line are the polygon from EAGLE. I can't hide the polygon line somehow, so they are still there. In the editing I added the zoom in of MCU layout. You can see the polygons are used for separating power pins and the power plane. You mentioned about the clearance of trace/copper. the manufacture can make 5 mils clearance, and I set 6 mils in the DRC, after running the DRC, it didn't give errors. So I believe it is okay. FYI. the grid is set to 25 mils as scalar. \$\endgroup\$ – MinShu Huang Jul 8 '18 at 9:47
0
\$\begingroup\$

220 ohm pull-up on NRST is too strong. Usually there is no pull-up at all, as the chip contains an internal pull-up. But I would leave the place for the resistor but not mount it so maybe a 10k can be put there later if necessary.

Don't put both pull-up and pull-down on BOOT0 pin. If you don't plan on using the built it bootloader and will only program via JTAG/SWD then you can just ground the BOOT0 pin or leave the 10k there.

\$\endgroup\$
  • \$\begingroup\$ Hi Justme, thanks for replying this old thread. For the pull-up and pull-down for BOOT0, they are optional, and only one of them will be placed, I am not intending to place both. But still thanks to pointing it out. And I will look into the internal pull-up for the NRST pin, thank for your advice! \$\endgroup\$ – MinShu Huang Nov 15 '18 at 7:18

Your Answer

By clicking "Post Your Answer", you acknowledge that you have read our updated terms of service, privacy policy and cookie policy, and that your continued use of the website is subject to these policies.

Not the answer you're looking for? Browse other questions tagged or ask your own question.