USB powered device with multiple Decoupling Capacitors

Question

I have a USB powered device with multiple IC's. From what I've read it's standard practice to use a combination of multiple range capacitors for decoupling each individual IC, with the smallest being as close as possible and larger capacitors not too far away.

However, I'm running into a dilemma:

According to this source, the maximum allowed decoupling capacitance for a USB device is 10uF. With several IC's all having a combination of 0.1uF and 2.2uF/4.7uF decoupling capacitors, I'm easily exceeding this limit because they're all in parallel.

The only solution I can think of is to reduce/eliminate the larger decoupling capacitor and/or try to clump a few IC's larger decoupling capacitors together while keeping the smaller decoupling capacitors close to each IC.

In my mind neither of these solutions seem ideal. What is the recommended decoupling layout for multiple IC's on a USB powered device?

The theoretical power consumption of all the IC's under use is still below the limit that can be supplied via USB 2.0.

Answer 1

While not exactly what you're looking for, I have used power-management ICs to accomplish this. For instance, the TPS2113APW. I prefer this specific chip because it allows me to make dual-powered devices that can operate with either a wall-wart or off the USB, automatically preferring wall-power if it is available.

If you don't need dual-powered, you could use something like the MIC2545A

Ultimately, any capacitance "behind" the power-management IC (i.e. hooked up to the IC outputs) isn't "seen" by the USB; the bus only sees the capacitance "in front of" the IC (i.e. hooked up to IC inputs).

You still have to worry about inrush current - the "plus any capacitive effects visible through the regulator" part of the spec - but those ICs also have variable current limiting. Figure out the parallel resistances that you need to have 100 mA limitation and 500 mA limitation (and optionally n mA limitation if you want to limit wall-power), and then use FETs to short out the resistors as needed to enable various limitations.

Through these chips, I have attached PCBs with several hundreds of uF to the USB, and a DMM set to fast current max verified that the inrush during attachment did not exceed 100 mA.

Answer 2

A USB device cannot present more than 10uF of capacitance when connected. This does not necessarily mean that you can only have 10uF of capacitors, it means that you need to limit the inrush current to that required to charge a 10uF upon connection. From the USB specification:

The maximum load (CRPB) that can be placed at the downstream end of a cable is 10 μF in parallel with 44 Ω. The 10 μF capacitance represents any bypass capacitor directly connected across the VBUS lines in the function plus any capacitive effects visible through the regulator in the device. The 44 Ω resistance represents one unit load of current drawn by the device during connect.

Furthermore:

If more bypass capacitance is required in the device, then the device must incorporate some form of VBUS surge current limiting, such that it matches the characteristics of the above load.

As you probably know, your device is allowed to draw 1 power unit, or 100mA, upon connection without any negotiation.

If I was designing a high power USB device then I would:

A. Live with the 10uF requirement, such as if I'm using a switching power supply or if my VDD is going to be 3.3V

or

B. Use a "soft start" circuit such as a 47 ohm resistor in series with my enormous bulk capacitor. Use a comparator to sense the voltage across the bulk capacitor. When the voltage is within 100mV of the USB bus voltage then have the comparator turn on a P-MOSFET that shorts the 47 ohm resistor.

Answer 3

The 100 nF ones are the most crucial. Be sure to place those and like you say as close as possible to the pins.

2.2/4,7 µF to place in parallel is a high value, and shouldn't be required in a properly decoupled power supply. Especially not on each IC. Here the power supply will be some distance away, and then a capacitor of a few µF is strongly recommended. Use the highest value you still can afford after subtracting the 100 nFs, and place that close to the IC which will draw the most current, unless that would be the other end of where the USB enters the PCB. Then you'll have to compromise: in the path from the USB connector, and not too far from the biggest current consumers.

Answer 4

The "maximum capacitance across the Vbus pin" rule is intended to keep the Vbus voltage from dropping low enough to reset the other USB devices whenever a new USB device is plugged in.

I've seen a few USB devices that only need a ferrite bead to keep the inrush current within specs. They connect only 2 things to the Vbus pin of the USB connector: the 1uF minimum VBUS decoupling capacitance directly across the Vbus and GND pins of the USB connector, and a ferrite bead that supplies power to the rest of the device. That allows them to use a net capacitance of slightly more than 10 uF on the other side of that ferrite bead.

Most of the schematics for USB-powered devices that I've looked at have a voltage regulator that converts between the 4.45 V to 5.25 V from the USB host to the 3.3 V used by all the chips on the device. Using a voltage regulator with a "soft start" circuit keeps the inrush current within specs; that enables the designer to put any amount of capacitance on the output of the regulator -- between 3.3 V and GND -- without any problems on the USB side.