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I'm in the process of creating a RAM module for a breadboard computer I'm making. The RAM I've decided to use is the AS6C62256A SRAM chip, in 32K x 8. Here's the datasheet: https://www.alliancememory.com/wp-content/uploads/pdf/AS6C62256A.pdf. I'm quite new to this field, and don't have much of an idea on how to access the memory. At first I assumed that I would have to simply set the inverted write line to low in order to write data to the current address, but there must be something wrong with the timing. I've looked at the timing diagrams, but have no idea what they mean. Could anyone give me some step-by-step instructions on how to write data to this chip?

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  • \$\begingroup\$ Did you activate any appropriate chip enables? What are you trying to write to it from, some manual array of switches or a processor? If so which one? Please detail how you generated RAM control signals from processor control signals. \$\endgroup\$ Commented Jul 8, 2018 at 1:02

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Here's an example timing diagram from the datasheet:-

enter image description here

The traces are similar to what you would see on an oscilloscope. Address and data lines are shown both high and low at the same time, representing multiple bits with (possibly) different logic levels. A line in the middle represents a 'high-z' or 'floating' signal. hatched lines are 'don't care' signals that can go high or low randomly without affecting operation.

To write data to the RAM:-

  1. the address lines must all be valid and stable (not changing) during the entire write cycle.

  2. W is brought low to start the write cycle. E must then be held low until W goes high again.

  3. External input data (DQi input) must be placed on the data bus and held stable for at least tSU(D) before W is pulled high, and held stable for tH(D) afterwards. During this time the RAM data outputs (DQi output) are 'high-z' (open circuit) allowing the input data to be on the bus without contention (the diagram shows two separate traces for clarity, but they are combined on the data bus).

  4. G can be either high or low during the write cycle (it must be held low to enable the output buffers when reading the RAM).

In the other type of write cycle ('E controlled') the roles of W and E are reversed. In practice this means that the write operation is completed by whichever one is raised first.

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I've looked at the timing diagrams, but have no idea what they mean. Could anyone give me some step-by-step instructions on how to write data to this chip?

Timing diagrams are precisely the instructions you are looking for. For every operation your memory controller must drive the signals in accord with provided timing diagrams in precisely the order shown.

As usual, there might be several options how to perform function. Below is the timing diagram for ^G-^E controlled READ operation

enter image description here

The diagram means that your controller must assert an address first, then assert E=low, then assert G=low, all after a minimum delay of Tsu. Then the valid data (memory content) will appear on data bus after time Ta. Before that time (Ta) the data bus can have some garbage (grey area on the diagram), which your controller should ignore.

After G and E are deasserted, your controller can remove/change the address to a new one, but the valid data are expected to stay for Tdis time before the memory IC turns the bus into high-impedance state (there could be several IC on the bus). That's it. For WRITE cycle it is similar, but a little more complicated.

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