I designed a two layers PCB for an AVR. The board would communicate with other peripherals(sensors, a micro SD card and so on) via SPI, I2C, and UART. The maximum speed on the PCB should be associated with the 16Mhz crystal oscillator and SPI bus. Since it is first time for me to design a PCB I wanted to ask if there is any big issues in my layout. More specifically, I wanted to know about the following points.
(1) the numbers/spacing of GND VIAs (related to the area "1" in the image)
I placed VIAs every 2mm in the GND plane, just because I heard it is helpful to have as many GND VIAs as possible to reduce GND plane inductance. But is the spacing of 2mm good enough or crazy(too many VIAs)? Even though it's a low speed device board, I wanted to make the design reasonable.
(2) having power planes on both of the layers (area "2" and "3")
The area "2" is the voltage output from a switching regulator. The expected current is lower than 0.5A. The area marked with "3" is the voltage dropped through a Schottky diode. For each of the areas I made copper pours on both layers to decrease inductance/resistance. However, on the bottom layer I have ground rings around these power planes. Would it be better to just have the power planes on one layer and increase the area of the GND plane?
(3) a power track separating GND planes
On the bottom layer (Green color), I have two GND planes almost separated by a 1cm thick 5V track in the center. I connected the left side and right side of the GND nodes around the track using the GND planes on the top layer. Therefore I have a chain of GND planes. I changed the routing method many times but could not find a better way of doing this. Is such track okay in general?
I'm afraid that my decisions on the track width, spacing, area assign are all based on only qualitative tips from internet. It would be appreciated if one could recommend a well associated literature..