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I designed a two layers PCB for an AVR. The board would communicate with other peripherals(sensors, a micro SD card and so on) via SPI, I2C, and UART. The maximum speed on the PCB should be associated with the 16Mhz crystal oscillator and SPI bus. Since it is first time for me to design a PCB I wanted to ask if there is any big issues in my layout. More specifically, I wanted to know about the following points.

(1) the numbers/spacing of GND VIAs (related to the area "1" in the image)

I placed VIAs every 2mm in the GND plane, just because I heard it is helpful to have as many GND VIAs as possible to reduce GND plane inductance. But is the spacing of 2mm good enough or crazy(too many VIAs)? Even though it's a low speed device board, I wanted to make the design reasonable.

(2) having power planes on both of the layers (area "2" and "3")

The area "2" is the voltage output from a switching regulator. The expected current is lower than 0.5A. The area marked with "3" is the voltage dropped through a Schottky diode. For each of the areas I made copper pours on both layers to decrease inductance/resistance. However, on the bottom layer I have ground rings around these power planes. Would it be better to just have the power planes on one layer and increase the area of the GND plane?

(3) a power track separating GND planes

On the bottom layer (Green color), I have two GND planes almost separated by a 1cm thick 5V track in the center. I connected the left side and right side of the GND nodes around the track using the GND planes on the top layer. Therefore I have a chain of GND planes. I changed the routing method many times but could not find a better way of doing this. Is such track okay in general?

I'm afraid that my decisions on the track width, spacing, area assign are all based on only qualitative tips from internet. It would be appreciated if one could recommend a well associated literature..

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  • \$\begingroup\$ 2mm is borderline crazy if your frequencies are in the order of 16 MHz. 16 GHz: different story. \$\endgroup\$ – Marcus Müller Jul 8 '18 at 9:43
  • \$\begingroup\$ and for whether you need power planes: grab one of the thousands of PCB trace width calculators. For 0.5 A, you hardly need a trace wider than one third of a mm (depending on how much voltage drop you're willing to tolerate). Certainly not something that requires a plane! \$\endgroup\$ – Marcus Müller Jul 8 '18 at 9:44
  • \$\begingroup\$ So, instead of going the "I read somewhere I should be doing XYZ", I'd recommend searching this site for XYZ and getting actual formulas for when what's appropriate. trace width simply is a matter of trace resistance, and the shorter your trace is, the less that matters, for example. Same goes for vias: albeit putting them in parallel will certainly reduce the inductivity, it really doesn't make that much of a difference for a low-speed board. \$\endgroup\$ – Marcus Müller Jul 8 '18 at 9:48
  • \$\begingroup\$ @MarcusMüller You're right. I have been searching for such quantitative explanations. \$\endgroup\$ – Nownuri Jul 8 '18 at 10:25
  • \$\begingroup\$ @MarcusMüller would it still help minimize EMI to have such large density of GND VIAs? Near the board I will install a very sensitive magnetic field sensor. \$\endgroup\$ – Nownuri Jul 8 '18 at 10:41
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Power planes are almost always a waste of real estate, and certainly on a board with only 2 layers. Track the power, let signals share the space.

Breaking a ground plane, that's if there's only one, is almost always a no-no. If you're going to the bother of using a ground plane, use a whole one. You don't need to use two for this speed of board. If you do want to run a track through the ground, then stitch the ground together on the other layer.

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  • \$\begingroup\$ Thanks! I didn't mean I want to separate analog/digital ground planes. I just needed to stitch several GND planes, due to the signal tracks separating my GND plane. \$\endgroup\$ – Nownuri Jul 8 '18 at 10:20
  • \$\begingroup\$ I'm sorry that I might use wrong terms. By the power/GND plane I meant the copper pour on top/bottom layer. \$\endgroup\$ – Nownuri Jul 8 '18 at 10:28

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