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I've created a block ram generator(single port ROM) in vivado using a coe file in verilog. I'm able to read the values one at time using continuous statement(able to instantiate rom block once a clock pulse). Here is my snippet:

module coedata(clk,rst,a);
input clk,rst;
output  [31:0]a;
wire[12:0]addra,out;
wire [31:0]douta ;
count c1(clk,rst,out); // just gives count in 'out' to access address(addra)
assign addra=out;
blk_mem_gen_0 your_instance_name (
  .clka(clk),    // input wire clka
  .addra(addra),  // input wire [12 : 0] addra
  .douta(douta)  // output wire [31 : 0] douta
);
assign a=douta;
endmodule

This is ok. I can read value through instantiating once a clock. But I want to store all these values into 2D wire such as [31:0] a[0:100].I want all the values to be available in one clock pulse.(Just assume we have created a sufficient ROM block)

module coedata(clk,rst);
input clk,rst;
reg  [31:0]a[0:99];
wire[12:0]addra,out;
wire [31:0]douta ;
count c1(clk,rst,out,i); // just gives count in 'out-binary' to access,'i-integer' address(addra)
assign addra=out;
blk_mem_gen_0 your_instance_name (
  .clka(clk),    // input wire clka
  .addra(addra),  // input wire [12 : 0] addra
  .douta(douta)  // output wire [31 : 0] douta
);
assign a[i]=douta;
endmodule

It is saying that 'i' is not a constant.

Thanks in advance.

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  • \$\begingroup\$ This sounds like an X-Y problem. What are you ultimately trying to do? \$\endgroup\$ – alex.forencich Jul 9 '18 at 9:05
  • \$\begingroup\$ I'm trying to create data block where we can use all data at time to perform computations just like in any other platform. \$\endgroup\$ – Sandeep I Jul 9 '18 at 10:33
  • \$\begingroup\$ So why are you using a RAM instead of just a bunch of registers? \$\endgroup\$ – alex.forencich Jul 9 '18 at 16:00
  • \$\begingroup\$ I used BLOCK RAM GENERATOR to get values from the COE file in Vivado. \$\endgroup\$ – Sandeep I Jul 10 '18 at 4:49
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Firstly, review your use of terms, it's quite important when using a HDL that you are aware of what you are describing. You can't store data in a wire - a wire is literally just a connection between two points.

Secondly, you need to start thinking about how your code could be converted to hardware. Without understanding the underlying hardware you are trying to describe, it is very difficult to use a HDL.

You're main problem here is that the entire contents of a block RAM cannot be read in a single cycle, unless it has an address width of zero (i.e. it is configured as Nx1). This is because the address line selects which element in the RAM is being read, and this address can only take one value in any clock cycle. This is the same reason that when programming software, you can't access every element in an array simultaneously.

In your case, in order to read the entire contents, you would need to have a RAM that was 3232x1. However there are no FPGAs that I know of which have block RAM memories with a data port width of 3232 bits. You could instantiate a 3232x1 memory using discrete registers (e.g. reg [3231:0] mem;).

If you want to use a 2-D block RAM, you need to describe a circuit that reads from the block RAM one address at a time. Each clock cycle you read an address, and then have to do something with the data, such as storing it in another register, performing some calculation with it, etc.

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  • \$\begingroup\$ Very nice answer. \$\endgroup\$ – Michael Karas Jul 9 '18 at 9:09
  • \$\begingroup\$ Thanks sir. yes I forgot to declare the storing variable as register. Now I'm able to retrieve the data from the ROM into the 2D RAM (retrieved one element once a clock pulse). \$\endgroup\$ – Sandeep I Jul 9 '18 at 11:21

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