0
\$\begingroup\$

I am trying to learn Verilog and was curious why my FPGA's block ram seems to provide the data that I request instantly. I was expecting that there would be some number of clocks that I would need to wait before my results would be available.

On a traditional computer's CPU, the only data available immediately is whatever is stored in a register correct? Data stored in caches or in ram would need to be fetched into a register before it can be operated on right? Are these block ram objects just implemented via registers on the chip?

Thanks

\$\endgroup\$
2
  • 2
    \$\begingroup\$ Open the specs of your FPGA block RAM and look at the timing diagrams. \$\endgroup\$
    – Eugene Sh.
    Jul 9, 2018 at 18:01
  • 3
    \$\begingroup\$ "On a traditional computer's CPU, the only data available immediately is whatever is stored in a register correct?" Incorrect. For example a L1 cache memory can provide data at the end of a single clock cycle. \$\endgroup\$
    – Oldfart
    Jul 9, 2018 at 18:21

1 Answer 1

1
\$\begingroup\$

Did you instantiate a primitive, generated IP, or infer it with an array?

IP typically has a choice for registered output or not.

If a primitive or inferred, you decide whether to register it (clocked process) or not in your RTL. The primitive is typically an asynchronous output, save any vendor-specific attributes that may be associated with it.

As @EugeneSh. said, The data sheet will tell you everything you need to know.

Data stored in caches or in ram would need to be fetched into a register before it can be operated on right?

You do not need to register a signal to operate on it... Depends on the situation. For reading memory, I probably would.

Are these block ram objects just implemented via registers on the chip?

You can choose to "push" memory into registers during synthesis, but, if you have RAM available, typically you would use the RAM (and the tool would default to implement that way too... especially if you used a primitive). The data sheet will tell you how much RAM you have, and how it is arranged. The synthesis report will tell you how it was implemented.

To make life easy, I would just infer RAM with an array.

\$\endgroup\$
2
  • \$\begingroup\$ I am using generated IP. Can you elaborate on what you mean by "registered"? Does providing a clock input mean it is "registered" to that clock? \$\endgroup\$
    – NeilMonday
    Jul 9, 2018 at 18:51
  • 1
    \$\begingroup\$ In terms of generated IP, there typically is an option for "registered out" via the GUI, which essentially wraps the RAM and puts a register on the output... or, it could be a manual assignment to an attribute. When I say, "register", I mean a non-transparent flip-flop (D-FF), that uses a clock to move (register) the value. i.e. from your RAM output to a "clock-cycle-later signal", seemingly, your output, or the signal you want to operate on \$\endgroup\$
    – CapnJJ
    Jul 9, 2018 at 19:03

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.