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I've got an ADC that requires me to send it 20 clock pulses when requesting to read data out of its internal register (after I've triggered it to read data from my sensor).

I was able to simulate this just fine in ModelSim but I'm new to Verilog and didn't realize that I would run into problems during synthesis when creating the pulse train like this:

reg [4:0] counter = 5'b10100;
parameter counter = 0;

always (posedge clk and negedge clk) 
  begin
   if (counter > 0)
     begin
       counter <= counter - 1;
       serial_out <= ~serial_out; 
     end
  end

I tried splitting this into 2 always blocks: one which sets serial_out to 1 on a posedge clk and another which sets serial_out to 0 during negedge clk, both checking if the counter is greater than 0. This is problematic because I'm attempting to drive counter in two places and get errors stating "can't resolve multiple constant driver for net counter .."

Perhaps there is a better way to do this?

I've seen some posts suggesting to double the clk frequency to read the data off of the posedge of the clock. This would work but I need to keep the clock at 30 MHz (can't go to 60 MHz for other reasons).

How would you suggest that I conditionally route/replicate 20 pulses of my always-on periodic 30 MHz input clock to an output pin?

Any help will be greatly appreciated.

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  • \$\begingroup\$ You need to use a gated clock. electronics.stackexchange.com/questions/352464/… \$\endgroup\$
    – Oldfart
    Jul 9, 2018 at 19:18
  • \$\begingroup\$ Thanks I just reworked my FSM and incorporated a gated clock. The simulation checks out. I think I've got a good pulse train now to work with when I do my synthesis. \$\endgroup\$
    – reacher33
    Jul 19, 2018 at 20:50

1 Answer 1

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I would suggest using an output DDR flip flop. How you implement that depends on what FPGA you're using. For Xilinx, it would be an ODDR or ODDR2 primitive. For Altera, it's ALTDDIO_OUT.

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  • \$\begingroup\$ I'm using a D flip flop with the output going into an AND gate using an assign statement. The simulation checks out. I'd like to drive a GPIO pin directly with this pulse train (serves as a serial clock). I see that you mention using ALTDDIO_OUT. \$\endgroup\$
    – reacher33
    Jul 19, 2018 at 20:56
  • \$\begingroup\$ Just because the simulation checks out doesn't mean it will work nicely on the FPGA, especially in terms of IO. \$\endgroup\$
    – alex.forencich
    Jul 19, 2018 at 20:57
  • \$\begingroup\$ OK, I'm new to this. Why is ALTDDIO_OUT required vs having a D flip flop inferred though some non-blocking statements during synthesis? I'm using Quartus Prime BTW. \$\endgroup\$
    – reacher33
    Jul 19, 2018 at 21:22
  • \$\begingroup\$ The ALTDDIO_OUT is dedicated logic that switches between two signals when the clock changes. You could do the same with flip flops if they were clocked at the double frequency since you need to react to the falling clock edge, but the dedicated logic wins out as you can just feed it two trivial signals ('1' to be transmitted after a low→high transition, and '0' after a high→low transition). \$\endgroup\$
    – Simon Richter
    Jul 19, 2018 at 21:43
  • \$\begingroup\$ The problem is how the FPGA is designed. The output pins can generally be driven either from the fabric logic or from a flip flop. The delay from a flip flop is constant and predictable. The delay from fabric logic is not and will vary depending on the logic, the placement, and will vary from device to device. The problem is not the flip flop, the problem is putting logic between the flip flop and the pin, especially if you want to maintain a specific timing relationship between that pin and other pins that may be directly driven by flip flops. \$\endgroup\$
    – alex.forencich
    Jul 20, 2018 at 0:24

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