Choosing a crystal and load capacitors for micro controller

Question

I'm trying to pick a crystal and load capacitor combination for the atmel UC3C series micro controller. The target CPU clock I'm shooting for is close to the max frequency of 66 MHz.

Here's the configuration I think would best achieve this goal:

A 11MHz crystal is attached between XIN0/XOUT0 with the appropriate load capacitors. Then use the PLL to multiply the frequency by 6. Use the PLL 66MHz as the cpu clock with no division.

Now here's where I have a few questions:

I've spec'd out a variety of 11MHz crystals. All of them have 50ppm frequency stability and 30ppm frequency tolerance. However, there are various ESR. According to this source the ESR represents roughly the bulk losses in the crystal so a lower ESR value would be the better choice. Correct?

Is there a significant difference between how I arrive at the CPU clock 66HMz frequency?

I have a few choices in addition to my original choice of a PLL multiplier of 6:

1. Multiply 11MHz by 12, then divide by 2 for a PLL output of 66MHz. No CPU clock divider.
2. Multiply 11MHz by 24 (multiplier = 12, divider = 0). CPU clock divider of 4.
3. Multiply 11MHz by 12, PLL divider = 1 for 132MHz PLL output. Use a CPU clock divider of 2.

All of these appear to be equally valid minus the level of code complexity to achieve each choice. Should I stick with my current "simplest is best" assumption, or do one of these other solutions create a better cpu clock?

All of the crystal I've found at 11MHz require either a load capacitance of 18pF or are in series. Is there any reason to choose one over the other? I can't tell anything different between the specs (same frequency tolerance/stability, same ESR, roughly same temperature range) Atmel's documentation only shows parallel crystal configurations.

If I do end up using a parallel configuration, how close should the load capacitors be to the specified load capacitance of the crystal?

Atmel's datasheet provides an equation for calculating the value of each load capacitor:

$$ C_{LEXT} = 2(C_L – C_i) – C_{PCB} $$

C_i is provided in the datasheet as 1.7pF. I'm unsure how to calculate C_{PCB}, but I would imagine it is greater than 0. This means that C_LEXT is at most 32.6pF. There are some 30pF, 32pF, and 33pF 1% C0G capacitors. I would think that the 30pF capacitors are the best choice because they are still relatively cheap compared to the 32pF capacitors, and don't exceed the 32.6pF limit as the cheapest 33pF capacitors. Am I right in my assumptions and conclusions?

Finally, is this a good setup? Are there other frequency crystals I should consider researching?

Answer 1

My seat-of-the-pants understanding for load capacitors (corrections invited) goes like this:

When a crystal is cut for a certain load capacitance, it is measured with that capacitance across it during final factory trimming. There is nothing magical about the value. It is simply a way of saying, that if you design your circuit to present that same capacitance, then your crystal will be within the stated (.005% or whatever) tolerance.

So, you add up all the capacitance in your circuit, and then add in what's needed to bring it up to the spec. We'll use your numbers. The stray capacitance due to the traces on the board obviously will vary with the board, so let's guess 1.3 pf. A number I made up, to go with the capacitance of the microprocessor's oscillator, stated to be 1.7 pf. So, we've got 3 pf in parallel with the crystal. The crystal wants 18pf, so we have to make up the 15 pf difference with discrete parts.

Since the two load capacitors are in series (Gnd->cap->xtal->cap->Gnd), we double the cap value to 30pf. Two 30 pf caps in series give us the 15 pf we're looking for.

Note 1. I tried searching for typical PCB stray capacitance. It was all over the map. Suffice it to say, that as the hardware gets smaller, the capacitance will keep getting smaller. A lot of typical values claimed less than 1 pf.

Note 2. If there is more capacitance than spec, the crystal will oscillate at a lower frequency than specified. If there's less, then it's higher. You can see, that if you want to trim the oscillator to spec, it's easier to shoot for a lower capacitance and add some later, than to try the opposite.

Note 3. For fun, look up "gimmick capacitor".

Note 4. My "seat of the pants" explanation is sufficient as an introduction, and this technique works in many cases, but not everywhere. For a more in-depth look at the EE principles behind those capacitors, see this answer.

Answer 2

I'm not the guy to ask about load caps, but I can give you some help with the PLL settings.

The different multiplier/divider settings might seem to give you the same end results, but they are not all equivalent. If you look at figure 8-2, page 85, in the datasheets you will see a simplified diagram of the PLL. What you have to know is that each signal in that PLL has both a minimum and maximum frequency. The input and output of the CPU divider also has a max frequency.

The trick in configuring any PLL is to get the various settings correct for the output frequency that you want without violating any of the min/max frequency limits.

In the datasheet, Table 40-11, Page 1257, lists the PLL specs. Output frequency range of 80 to 240 MHz. Input freq of 4 to 16 MHz. Note that the input frequency is the input to the PLL, after the input divider.

I can also tell you that you want the PLL input frequency to be as high as possible. Doing this will give your PLL more stability and less jitter.

In each case, the input divider will be divide by 1 since this will give us the highest input frequency within the allowable range or 4 to 16 MHz.

The maximum multiplier value you can use is 21. Because 240 MHz / 11 MHz = 21.82. If the multiplier was set to 22 then the output frequency will be higher than the 240 MHz max. So immediately we can throw out the 24x option.

Table 40-11 lists the maximum CPU clock frequency as 66 MHz. What I am confused about is if that frequency is before the CPU clock divider, or after. It probably says somewhere in the datasheet, but I don't really feel like reading all 1,316 pages today. If the 66 MHz max is on the input of the divider then you must use your option #1: PLL output is 66 MHz and CPU divider = 1.

But if the 66 MHz limit is post-cpu-divider then option #3 is also valid. Option #3 might have other benefits when clocking other peripherals, but that is beyond the scope of this answer.

When in doubt, it seems like option #1 is your best choice.