Like this one, which does 1.49 DMIPS/MHz. Even with pipelining there's still only 1 execute stage per cycle isn't it?
DMIPS and MIPS are not the same. DMIPS stands for "Dhrystone MIPS", and it's a standard for comparing different microcontrollers/microprocessors' performances across different instruction sets. The standard is not so new anymore(*), so what the reference processor could do at 1 DMIPS/MHz in 1 second may take a more advanced controller 670 ms at the same clock speed, just because it will do some actions in 1 instruction whereas the other controller may need 2 instructions, or an instruction requiring more machine cycles.
A 16-bit architecture, for instance, will typically have a better Dhrystone performance than an 8-bit architecture, and a 32-bit, like the one you're referring to, even more.
(*) m.Alin refers to the more recent CoreMark benchmark. Note that this is written in C, so actually you're also including the compiler's performance in the result (just like Dhrystone, BTW).
DMIPS is a relative measurement rather than absolute. As opposed to MIPS, it actually measures how quickly the uC can do something useful instead of just how fast it executes instructions.
Like any benchmark it has it's limitations, but a simple way of looking at it is how quickly it can complete the benchmark code compared to a VAX 11/780 (a 1 MIPS machine)
So for example if your uC completes the benchmark 100 times faster than a VAX 11/780, you have a 100DMIPS machine. If it runs at 100MHz, then it's rated at 1 DMIPS/MHz.
Note that the advertised DMIPS is usually unattainable in normal use, especially on large uCs with flash speed, prefetch, wait times/misses, etc. Here is a good discussion of the PIC32 DMIPS performance. This link has some Dhrystone code for microcontrollers.