I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges.

  1. tclock >= Propagation delay + tsetup + thold
  2. tclock >= Propagation delay + tsetup
  3. tclock >= Propagation delay + Max(tsetup, thold)

Which one of them is right? From my understanding, it should be the first version, but I've found some answers that say that hold-time doesn't change the clock speed.

  • 3
    \$\begingroup\$ Most flip flops have a minimum clock speed of 0 Hz. \$\endgroup\$
    – Andy aka
    Commented Jul 11, 2018 at 13:00
  • \$\begingroup\$ Ah my bad, I was thinking of the minimum clock period. \$\endgroup\$
    – Anicx
    Commented Jul 11, 2018 at 13:07

2 Answers 2


The ambiguity comes from the fact that the meeting the hold time requirement depends on the propagation delay.

If you assume that the propagation delay of the FF is always longer than the hold time, then the propagation delay assures that the hold time is met and tclock >= tprop + tsetup.

It would be unusual for the propagation delay of a FF to be shorter than the hold time.

There is of course extra complication caused by the fact that propagation delay, setup, and hold change with voltage and temperature, and you need to account for skew between the clocks at the source and destination FFs.

  • \$\begingroup\$ So it's more like: tpropagation > thold AND tclock >= tprop + tsetup? \$\endgroup\$
    – Anicx
    Commented Jul 11, 2018 at 13:34
  • 1
    \$\begingroup\$ Yes. In the unusual case of tprop < thold, you would need to add delay to the FF output, which would effectively increase tprop. \$\endgroup\$
    – crj11
    Commented Jul 11, 2018 at 13:39
  • \$\begingroup\$ "The ambiguity comes from the fact that the meeting the hold time requirement depends on the propagation delay." Only if the Q of the FF is involved in changing the state of the D input. This is an important distinction in some analysis cases. \$\endgroup\$ Commented Jul 11, 2018 at 14:35
  • \$\begingroup\$ @MichaelKaras If a FF does not affect the D input of the destination FF, then there is no reason for it to be connected. It could be logically eliminated. Whether the FF state matters at a particular clock cycle is irrelevant, assuming that it matters at one or more clock cycles. Certainly, depending on the logic between the Q output and the D input, the propagation delay can depend on the system state. Perhaps that is your point? \$\endgroup\$
    – crj11
    Commented Jul 11, 2018 at 14:45
  • \$\begingroup\$ @crj11 - If you read my answer you should be able to get my point. When you say that the there is a "destination FF" then that is extending the analysis to a system of FF's and then that extends it to the second part of my answer. The single FF analysis can come into play when working with some circuit design where FFs are independently clocked from edges of async signals as opposed to the common clocking scheme. \$\endgroup\$ Commented Jul 11, 2018 at 14:57

If the flip-flop is being analyzed strictly on its own with regard to the CLK and the D inputs then the minimum clock period approaches the sum of the tsetup and the thold times. The propagation delay only comes into play if the outputs of the flip-flop determine the next state of the D input.

Now with that said most systems being analyzed will have an array of multiple flip-flops that all have their CLK inputs connected to a common clocking source. In addition the outputs of the various flops will be interconnected in some way, possibly including other combinatorial logic, to determine the next state values to the D inputs to the flops. In this case it is necessary that the propagation delay always be included in the analysis and that delay has to include more than just the delay, CLK to Q, of the flip-flop. The extra delay of additional combinatorial logic paths has to be added and in the cases of very high speed clocks the delay of the signals along the routing paths also has to be added.

In system level or state machine type analysis for minimum clock period it is common to consider the delays of all the flip-flops to be the same worst case specs so that each and every path through the logic tree does not need to be computed individually. This is also a reason that robust logic design always wants to be synchronous with respect to a common clock source so that analysis can be confined to clock to clock behavior.


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