I have come across a lot of posts which say that the initial block is not synthesizable in Verilog HDL. According to this appendix on synthesizable and non-synthesizable Verilog constructs (from the book Digital Logic Design Using Verilog by Taraate), the initial block is not synthesizable.

I prefer using a reset to initialize any content in memory blocks. But my friends are doing a gaming project where they set the initial positions (values) of blocks using an initial keyword (we're using a Nexys 4 DDR FPGA). It worked.

I really don't know what to say because I thought it was not possible. Can you please explain this to me? I'm using Xilinx Vivado.

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    \$\begingroup\$ My guess it works because you're using an FPGA. One generally just can preload the registers (and about everything) in those with the programming bitstreams. However, in 'real silicon', without a PoR circuit and reset magic, the registers may power up in just about any state they like. I don't know, it's just a guess. That said, I can't see why there couldn't be a silicon synthesizer that would do the PoR handling for you. \$\endgroup\$ Jul 11, 2018 at 13:21
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    \$\begingroup\$ I believed the same about the signal initialization and was surprised... But it looks like the tool vendors are feeling too free adding non-standard features which are doing more mess than order, if you ask me... \$\endgroup\$
    – Eugene Sh.
    Jul 11, 2018 at 13:54
  • \$\begingroup\$ Thanks @RichardtheSpacecat. But as Eugene Sh mentioned that vendors might have added these features and this varies with the tool we're using. \$\endgroup\$
    – Sandeep I
    Jul 12, 2018 at 4:30
  • \$\begingroup\$ Don't use reset to initialize memory bocks, this will result in using a very large number of registers instead of distributed or block RAM. \$\endgroup\$ Jul 12, 2018 at 8:32
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    \$\begingroup\$ @alex.forencich Is there any other way to initialize the content? Please let me know. \$\endgroup\$
    – Sandeep I
    Jul 12, 2018 at 10:49

1 Answer 1


Xilinx Vivado can synthesize initial blocks in some cases. For example, Vivado Synthesis Guide (page 145) shows how to initialize RAM contents.

reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
integer i;
initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;

According to page 147, $readmemb can also be used to initialize a RAM.

reg [31:0] ram [0:63];

initial begin
    $readmemb(“rams_20c.data”, ram, 0, 63);

If we talk about ASIC, Design Compiler doesn't synthesize* these blocks.

  • \$\begingroup\$ Yes. But they also used system function $readmemb for reading the data file which is not synthesizable. (Can we consider the immediate above example that you've mentioned for synthesis?) \$\endgroup\$
    – Sandeep I
    Jul 12, 2018 at 4:20
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    \$\begingroup\$ Your answer is very misleading...initial blocks in general are not synthesizable. These code examples are not synthesized in the normal sense of the word. Clearly, the FPGA can not access a RAM data file directly. The desired RAM contents are embedded in the bit stream for programming the FPGA before the FPGA is actually configured. \$\endgroup\$ Jul 12, 2018 at 11:14
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    \$\begingroup\$ Your first sentence is that "Vivado can synthesize initial blocks". This is not true in general but only for specific cases. I wouldn't use the word "synthesis" to describe initializing a RAM...to me, "synthesis" is the process of converting HDL to a specific hardware implementation. \$\endgroup\$ Jul 12, 2018 at 11:39
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    \$\begingroup\$ @ElliotAlderson I updated the sentence then. For "synthesis", I still disagree. In FPGAs, I don't see any difference between initializing a RAM or a LUT. If you say that we cannot use the word "synthesis" for RAM initialization, we should never use it for FPGAs at all. \$\endgroup\$
    – user154136
    Jul 12, 2018 at 11:57
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    \$\begingroup\$ As an additional comment, Intel PSG , former Altera, also supports initializing a memory using initial block. The reason, I think, is that both manufacturers wanted to provide tools to infer RAMs without having to resort to IP usage. And I think it is good, because inferred blocks are obviously more reusable than IP blocks. \$\endgroup\$ Mar 4, 2021 at 8:06

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