I have come across a lot of posts which say that the
initial block is not synthesizable in Verilog HDL. According to this appendix on synthesizable and non-synthesizable Verilog constructs (from the book Digital Logic Design Using Verilog by Taraate), the
initial block is not synthesizable.
I prefer using a reset to initialize any content in memory blocks. But my friends are doing a gaming project where they set the initial positions (values) of blocks using an initial keyword (we're using a Nexys 4 DDR FPGA). It worked.
I really don't know what to say because I thought it was not possible. Can you please explain this to me? I'm using Xilinx Vivado.