Is the initial block in Verilog sythesizable?

Question

I have come across a lot of posts which say that the initial block is not synthesizable in Verilog HDL. According to this appendix on synthesizable and non-synthesizable Verilog constructs (from the book Digital Logic Design Using Verilog by Taraate), the initial block is not synthesizable.

I prefer using a reset to initialize any content in memory blocks. But my friends are doing a gaming project where they set the initial positions (values) of blocks using an initial keyword (we're using a Nexys 4 DDR FPGA). It worked.

I really don't know what to say because I thought it was not possible. Can you please explain this to me? I'm using Xilinx Vivado.

Answer 1

Xilinx Vivado can synthesize initial blocks in some cases. For example, Vivado Synthesis Guide (page 145) shows how to initialize RAM contents.

reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
integer i;
initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;
end

According to page 147, $readmemb can also be used to initialize a RAM.

reg [31:0] ram [0:63];

initial begin
    $readmemb(“rams_20c.data”, ram, 0, 63);
end

If we talk about ASIC, Design Compiler doesn't synthesize^* these blocks.