For Ethernet PHY design, the MDI interface should be terminated. Then how about the MII/RMII or GMII/RGMII interfaces? I've seen some designs terminated them, and most not. There are some PHY chips even advertise they have integrated termination on chip, such as TI's DP83640.
MII runs at 25Mhz, so at that speed transmission line effects are usually not seen. RMII runs at 50Mhz which does need impedance matching and the DP83640 uses 50Ω matching so build your PCB traces for 50Ω if using RMII.
RGMII uses 2.5V CMOS or 1.8V HSTL at 125Mhz
You use HSTL if you have transceivers to do so, this also implies matching
2.5V CMOS will need to have a matched transmission line for whatever port it is being driven from (either microprocessor or FPGA) and the PHY