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I am having troubles determining when a capacitor is being charged or being discharged, never understood the concept when a capacitor is under going that process besides the fact when a Source is connected to a cap it will charged to said source, and once removed it will start discharging.

I am talking about more complicated circuit such as ones below.

Circuit Diagram: being questioned

schematic

simulate this circuit – Schematic created using CircuitLab

Positive Cycle Analysis :

schematic

simulate this circuit

Negative Cycle analysis

schematic

simulate this circuit

I understand the positive cycle is charging the capacitor through R1, and R2, however for the negative Cycle I have no idea what that capacitor is doing? I am not even sure if this analysis is right, but this is the only thing that makes sense to me.

This is suppose to be a rectifier circuit, where it charges on every cycle I guess? So maybe the negative cycle is charging the cap as well, but when is it being discharge?

I guess what I am trying to ask if that if a cap is charging or discharging How do one find the path it takes to be charged/discharge.

EDIT: With a bit more thinking I figured the capacitor is both charging and discharging in the same cycle both postive and negative. I am still confused on which path current takes for discharging, and charging. For example if you look at the positive cycle and its discharging, is the current flow opposite and if so does that make the diode forward bias again thus changing the topology of the circuit?

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  • \$\begingroup\$ Did it charge up past 1V on the positive cycle? \$\endgroup\$ – Ignacio Vazquez-Abrams Jul 12 '18 at 4:52
  • \$\begingroup\$ it doesnt charge past 1V?, not sure if I have the models right but in actuality the circuit is working fine. Just trying to understand whats going on with the cap as I need to know how the cap is discharging and discharging to improve attack and delay on - oncoming waveforms \$\endgroup\$ – Pllsz Jul 12 '18 at 5:00
  • \$\begingroup\$ I see, were my models correct? \$\endgroup\$ – Pllsz Jul 12 '18 at 7:09
  • \$\begingroup\$ Yes, for the positive cycle, the opamp cannot "close the negative feedback loop" because of the D1 diode is in reverse bias. Let us momentarily freeze the input signal. Now suppose we allow the input signal to rise. \$\endgroup\$ – G36 Jul 12 '18 at 7:25
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For the positive cycle:

Opamp output voltage is at negative saturation (positive voltage at inverting input). Hence we can remove the opamp from the circuit if we want to analysis the positive cycle.

Addtionolen you should notice that the signal period is:

\$t = \frac{1}{1\textrm{kHz}}=1\textrm{ms} \$

And this time is much less than the RC time constant

\$t = RC = 2\textrm{k}\Omega \cdot 470\mu\textrm{F} = 940\textrm{ms}\$

So, Vin won't affect the capacitor voltage much. We can say that this voltage is unchanged.

For example, if we have 1V across the capacitor and we set the Vin voltage at 0V

The capacitor will start to discharge with the time constant \$t = RC = 940\textrm{ms} \$.

And the current will flow in this path:

Upper capacitor plate ---> R1--->R2--->gnd--->lower capacitor plate.

And the opamp will don't have any influence in this process. Because the D1 diode is reversed biased due to the fact that the voltage at (-) input is positive (0.5V at the beginning of a discharge process) and opamp output at negative situation voltage.

And at the end of a discharging process when the capacitor voltage is almost 0V (after 5*RC). The opamp output will rise up to 0.7V. To forward based the D1 diode and kept the output voltage at 0V.

For the negative cycle,

The voltage at (-) input will now be negative. So the output will go into the positive direction and this will further forward biased the D1 diode.

And the capacitor will be quickly charged to this new voltage in the path:

Vcc--->opamp_internal transistor--->D1--->C1-->gnd.

The opamp will also provide a current for R1 and R2 resistors.

But now if you change the input voltage to -0.5V we encounter an interesting situation. The capacitor voltage is at +1V but the input signal is at -0.5V So, the opamp (-) input we see the positive voltage

(+1V - (-0.5V))* R1/R1+R2 + (-0.5V) = 1.5V/2 - 0.5V = 0.25V.

Therefore at this moment of time, the opamp output will go into negative saturation voltage and turn-off the diode.

And our capacitor will begin the discharge process in this path:

Upper capacitor plate--->R2-->R1-->Input signal source--->Gnd--->lower capacitor plate.

And we can find the discharge time

$$t = RC \cdot ln \left(\frac{V_{\infty} - V_{start}}{V_{\infty} - V_{end}} \right)$$

$$t = 940\textrm{ms} \cdot ln \left(\frac{-0.5V-1V}{-0.5V - 0.5V} \right) = 940\textrm{ms} \cdot 0.405 \approx 380\textrm{ms} $$

And once again as discharge process ends the op amps kicks-in into action. And ensures that Vout = 0.5V

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  • \$\begingroup\$ Thank you that actually cleared a lot of things up. Just curious is this a type "Upper capacitor plate ---> R1--->R2--->gnd--->lower capacitor plate" For the positive cycle? Should it be R2---->R1 instead? \$\endgroup\$ – Pllsz Jul 12 '18 at 18:04
  • \$\begingroup\$ Yep, a typo. It should be R2--->R1 \$\endgroup\$ – G36 Jul 12 '18 at 18:13
  • \$\begingroup\$ okay okay you actually made everything make sense SO essentially, Positive Cycle: Cap is being charged thru R1-R2 discharged thru R2- R1 Negative Cycle: Cap is being charged thru OP AMP->D1 and discharged thru R2 and R1 because when Vin hits back to ~0 the diode becomes reversed bias again \$\endgroup\$ – Pllsz Jul 12 '18 at 20:07
  • \$\begingroup\$ Can you change the charge time of the cap during the negative cycle as the R2 and R1 doesnt influence it? \$\endgroup\$ – Pllsz Jul 12 '18 at 20:10
  • \$\begingroup\$ So you want a quick discharge phase during the negative cycle? \$\endgroup\$ – G36 Jul 13 '18 at 4:38

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