1
\$\begingroup\$

So I can define a package with a generic - in this case, the package takes a size as a generic and defines a vector type of that size:

library ieee;
use ieee.std_logic_1164.all;

package vector_package is
    generic (
        size : integer);

    subtype vector_t is std_logic_vector (size - 1 downto 0);
end package;

Now I can instantiate that package within an architecture to create a signal of that vector type:

entity foo is
end entity;

architecture rtl of foo is
    package vp_4 is new work.vector_package generic map (size => 4);
    signal vector : vp_4.vector_t;
begin
end architecture;

But what I want is to use the vector type for a port signal. I would have expected to be able to do something like this, but it does not appear to be valid VHDL 2008:

package vp_4 is new work.vector_package generic map (size => 4);

entity bar is
    port (
        signal vector : out vp_4.vector_t);
end entity;

This is rejected by ModelSim 10.2c with the message (vcom-1136) Unknown identifier "vp_4". in the line containing signal vector : ....

Is there a way to use the type from the package for a port signal? I am aware of unconstrained types as an alternative, but they do not fit my requirements in the actual use case.

\$\endgroup\$
  • \$\begingroup\$ An expanded name - signal vector : out work.vp_4.vector_t or a use clause - use work.all; making vp4 visible in the entity declaration. \$\endgroup\$ – user8352 Jul 12 '18 at 13:08
  • 1
    \$\begingroup\$ See IEEE Std 1076-2008 13.1 Design units. A package instantiation declaration is a primary unit and doesn't share the same root declarative region with the entity declaration (12.1 Declarative region, "In addition to the preceding declarative regions, there is a root declarative region, not associated with a portion of the text of the description, but encompassing any given primary unit"). You've instantiated the package in the same resource library as the following entity declaration. \$\endgroup\$ – user8352 Jul 12 '18 at 13:44
  • \$\begingroup\$ @user8352 Indeed, work.vp_4.vector_t works. Would you convert your comment to an answer, so I can accept it? \$\endgroup\$ – Martin Herrmann Jul 13 '18 at 9:19
0
\$\begingroup\$

Credit for the answer goes to user8352 who provided the solution and some background. The vp_4 package is found in the work library and the following will work:

package vp_4 is new work.vector_package generic map (size => 4);

entity bar is
    port (
        signal vector : out work.vp_4.vector_t);
end entity;
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.