1
\$\begingroup\$

Can we declare Generate if-for statement?

module prac#(parameter m=3)
(input x, input[2:0]a,b,output[2:0]c);
wire [2:0]f[0:3];
genvar i;
generate
if(!x) begin : d2
    for(i=0;i<=m;i=i+1) begin:dd
    assign f[i]=(a & b);  end
end
endgenerate
endmodule

It is saying that 'x' is not a constant. I want to instantiate a module multiple times based on control signal. Here x is my control signal. Is it possible?

Thanks in advance.

\$\endgroup\$
  • \$\begingroup\$ What do you think your code should infer in hardware? \$\endgroup\$ – Tom Carpenter Jul 12 '18 at 11:12
  • \$\begingroup\$ What would be required to happen if the input x was zero, and then changes to one? \$\endgroup\$ – Tom Carpenter Jul 12 '18 at 11:13
  • \$\begingroup\$ Using x as an identifier seems like a very poor choice since that character also has special meaning. \$\endgroup\$ – Elliot Alderson Jul 12 '18 at 11:16
  • \$\begingroup\$ @TomCarpenter. Sir, sorry I didn't go for hardware at this time. I have all the data available and in that clock pulse itself I want to perform computation on all data points in parallel. x- indicates the data is available to perform operation. I'm learning verilog HDL and have seen the generate if and generate for statements which instantiate and create blocks without explicit instantiation of each one. Please let me know if I'm wrong and are there any other things I've to keep in mind while using instantiations \$\endgroup\$ – Sandeep I Jul 12 '18 at 11:30
2
\$\begingroup\$

What you have written is:

"If signal X is true I don't need any hardware.
If signal X is false I want to have some hardware which does..... "

Hardware either exists or it does not exist. It can't just disappear into nothing or appear out of nothing.

All you can do is have the hardware (always) present end then you can use it or not.

\$\endgroup\$
1
\$\begingroup\$

No, you can not control instantiation of modules at run time. Don't confuse a hardware description language with a conventional programming language. You must instantiate, once and for all, every module you will ever need. Your HDL code then specifies ways of controlling data flow and conditional access to the modules.

\$\endgroup\$
  • \$\begingroup\$ I have read that using Generate construct we can instantiate module multiple times which will create blocks of hardware. \$\endgroup\$ – Sandeep I Jul 12 '18 at 11:34
  • \$\begingroup\$ Yes, but that can only happen at compile time (or better, synthesis time). \$\endgroup\$ – Elliot Alderson Jul 12 '18 at 11:35
  • \$\begingroup\$ Then x can't be a "control signal" that changes after synthesis. x must be a constant value, which is what the tools are trying to tell you. \$\endgroup\$ – Elliot Alderson Jul 12 '18 at 11:44
  • \$\begingroup\$ yes. x is constant but it depends on the previous operations. As there is a data dependency I've used control signal which just indicates that the operation was completed and gives one otherwise zero. \$\endgroup\$ – Sandeep I Jul 12 '18 at 11:48
  • \$\begingroup\$ No! The value of x can not depend on anything that is not a constant known to the tools at compile time. The value of x can never, ever, ever change. \$\endgroup\$ – Elliot Alderson Jul 12 '18 at 11:51
0
\$\begingroup\$

Make X a parameter instead of an input. Inputs can change over time, parameters are fixed per instantiation.

You also need to assign something to F in an "else" branch.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.