I recreated and trying to understand for the sake of fun and learning the circuit that can be seen here on second page: Link . This is basically a 4-bit carry-lookahead adder, but there is one thing that I cannot understand. If there will be 1111 and carry bit will be 1, it looks like there is no way to pass a carry to the next unit. Turning carry bit on and off is irrelevant for the output (I mean here output information about carry). Maybe I'm missing something/recreated it wrong or some logic is in the "carry output" unit, anyone could explain it, and show how should connections between that kind of adders should look like? :)

You can download this circuit recreated in CEDAR Logic Simulator Here .



The carry input for each adder subunit (marked "PFA") is located on the bottom of the subunit schematic. It gets injected via the ripple carry subunit, which is duplicated for each adder unit.

Now I see what the issue is.

The reason the CLC has G and P outputs is for cascading into another CLC so that higher-order carries can be looked ahead (lookaheaded?). However:

If there are only four bits in the adder, then the logic circuit used for C1 can be used to generate C4 from these two outputs; we will later refer to the C1 logic block as OC (Output Carry) for generating the output carry from an adder, in this case, C4.

So, you need to duplicate the AND and OR gates at the LSb of the CLC in order to get C4 from G0-3 and P0-3.

  • \$\begingroup\$ It's hard for me to imagine the connections, do you maybe have some graphics of circuits (or links), or could make one based on my cdl file? That would help not only me :) . \$\endgroup\$ – Łukasz Zaroda Aug 21 '12 at 21:24
  • \$\begingroup\$ You mean the connection between C4 of the previous adder unit and C0 of the next? \$\endgroup\$ – Ignacio Vazquez-Abrams Aug 21 '12 at 21:27
  • \$\begingroup\$ Yep, exactly :) . \$\endgroup\$ – Łukasz Zaroda Aug 21 '12 at 21:59
  • \$\begingroup\$ But... that's... just a single wire... \$\endgroup\$ – Ignacio Vazquez-Abrams Aug 21 '12 at 22:00
  • \$\begingroup\$ Well, not in a case of my circuit, you will see, that there is ONE input for carry and TWO outputs besides of 4 bits, and yet in certain situation, carry is not outputting even if I think it should, hence my question. You should look at the circuit I'm referencing :) . \$\endgroup\$ – Łukasz Zaroda Aug 21 '12 at 22:25

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.