I am just a beginner in electronics, so please bear with me.
I am using a signal generator to get two channel output which are then fed to a FPGA based Mojo. The mojo is then connected to a computer which has a GUI, which shows me counts on two channels. The mojo has a 50 MHz clock cycle. The way it works is:
"The external signal from the signal generator is connected via BNC to 4 I/O pins on the FPGA. The signals that are captured are then digitized by Pulse Replicator Modules, which I think is also supposed to help in synchronization of external signal with the FPGA clock. The output signal is then sent to a comparator module which is like a 4-way AND gate;when the input is connected to the top-level Pin Register, an OR mask is used to hold a “1” on the channels the user wishes to ignore. "
Now, the problem is if I set my channel A to 10 MHz, my GUI shows that at least 100 counts are lost. Same for channel B. But, when it is a low frequency signal like let's say 5KHz, it shows 4999 and fluctuates around that value. What could possibly be the problem that I am losing counts? Is it because the clock cycles of the FPGA in the mojo and the signal generator asynchronous?
Edit: I have added how the signal is processed by the FPGA.