# gates operation in flip flop [closed]

The operation of logic gates in the flip flop is pretty confusing for me. If I am not wrong then the NAND and NOR gates provide output only when there are at least two inputs. But in case of the flip flop, the output of one gate is used as others input. Lets take SR flip flop for example. There are two NOR gates and each has its input form the output of another one. So both gates should not produce any outpu. Would be of great help if someone can figure out where I am missing the core idea.....Thanks

## closed as unclear what you're asking by The Photon, Dmitry Grigoryev, laptop2d, Charles Cowie, mkeithJul 19 '18 at 6:50

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• Why do you think that having the input of a gate coming from another gate means it "should not produce any output"? A gate will produce an output that depends on its inputs, regardless of what source is providing that input. – The Photon Jul 14 '18 at 5:57
• one of the inputs is a +5v lets say. And another one is the output of second gate. But the second gate requires two inputs as well and one of them is another ones output. The point is how does the next gate produce output when its 2nd input is still missing? – JuneStar_2918 Jul 14 '18 at 6:16
• It would probably help to pick either the NAND or NOR flip-flop, and include the schematic in your post so we are all talking about the same thing. – The Photon Jul 14 '18 at 6:46
• Note that logic gates are physical objects -- just because the inputs aren't 100% stable at the beginning doesn't mean the output doesn't exist. The gates will output high or low (or somewhere in between, but probably nothing crazy), regardless of what's happening at their input. This is not a function that blocks until all its arguments are evaluated, it is a circuit that always produces an output voltage, regardless of if the inputs are ready or not. – Persona Jul 14 '18 at 6:59

## 1 Answer

If I am not wrong then the NAND and NOR gates provide output only when there are at least two inputs.

You are wrong. Gates always produce an output. The output is high or low depending on the state of the inputs.

• The comment from the OP "how does the next gate produce output when its 2nd input is still missing?" shows the same misconecption: there is no such timing requirement. – Wouter van Ooijen Jul 14 '18 at 8:40