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Please help me understand the following paragraph in chapter CMOS Digital Logic Circuit from book"Sedra/Smith micro electronics circuit 6e".

An ideal VTC is one that maximizes the OUTPUT signal swing and the noise margins. For an inverter operated from a power supply VDD, maximum signal swing is obtained when VOL = 0 V, and VOH = VDD. Where VOL and VOH is the Output Low level and Output High level respectively.

But I thought the amplitude of OUTPUT signal swing is determined by the Bias point Q in the VTC transitional region (the linear section). and in my opinion what the above statement does is maximizing the INPUT signal swing (rather than output) because when VOL = 0 V, and VOH = VDD, the Noise Margin for both Low input and High input are maximized as Noise Margin is defined VOH - VIH = VDD - VIH for Logic High input signal, and VIL - VOL = VIL - 0 for Logic Low input signal. And a wider Noise Margin indicates better tolerance to noise signal at the input, therefor a greater headroom and legroom allowed for the input signal instead of the output signal.

What did I misunderstand here? How does conditions like VOL = 0 V, and VOH = VDD maximized the output signal swing?

thank you so much everyone.

Zheng

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    \$\begingroup\$ What is a VTC?? \$\endgroup\$
    – Andy aka
    Jul 15, 2018 at 14:50
  • \$\begingroup\$ @Andyaka Voltage Transfer Characteristic. \$\endgroup\$ Jul 15, 2018 at 16:56
  • \$\begingroup\$ It normally stands for "Voting To Close". \$\endgroup\$
    – Andy aka
    Jul 15, 2018 at 17:31

2 Answers 2

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Simply, Voh cannot be greater than Vdd. Likewise, Vol cannot be less than 0 (for a single-supply system referenced to ground). So the maximum and minimum possible are set by those two parameters, regardless of any other considerations.

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For digital design, you want to have the clearest distinction you can get between a logical '1' and '0' to maximize the noise margins. In any process that is powered between 0V and VDD, the best you can do is 0V for a logical '0' and VDD for a logical '1'. Whatever digital block you send this output into, these signals are the best you can do when it comes to noise margins.

But I thought the amplitude of OUTPUT signal swing is determined by the Bias point Q in the VTC transitional region (the linear section).

I am assuming point Q is the somewhere in the 1 to 0 transition.
You have to be careful that you don't confuse all this with analog design, where you sometimes treat the inverter as an analog amplifier. In that case the output does not typically reach VDD or 0V, and the output amplitude will be determined by the gain, ie. the slope in this transition region.

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  • \$\begingroup\$ Hi Sven B, thank you for responding to the question. I think, as you pointed out, I might confused the digital with analogue. Then my question would be "what's the output signal Swing in digital sense?" In the analogue amplifier design we want the signal swing get as far away from the upper/lower rail as possible. But it seems like the signal Swing has a different interpretation in digital Logic circuit design. thank you Sven B \$\endgroup\$
    – Jung_Zheng
    Jul 15, 2018 at 17:40

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