Please help me understand the following paragraph in chapter CMOS Digital Logic Circuit from book"Sedra/Smith micro electronics circuit 6e".
An ideal VTC is one that maximizes the OUTPUT signal swing and the noise margins. For an inverter operated from a power supply VDD, maximum signal swing is obtained when VOL = 0 V, and VOH = VDD. Where VOL and VOH is the Output Low level and Output High level respectively.
But I thought the amplitude of OUTPUT signal swing is determined by the Bias point Q in the VTC transitional region (the linear section). and in my opinion what the above statement does is maximizing the INPUT signal swing (rather than output) because when VOL = 0 V, and VOH = VDD, the Noise Margin for both Low input and High input are maximized as Noise Margin is defined VOH - VIH = VDD - VIH for Logic High input signal, and VIL - VOL = VIL - 0 for Logic Low input signal. And a wider Noise Margin indicates better tolerance to noise signal at the input, therefor a greater headroom and legroom allowed for the input signal instead of the output signal.
What did I misunderstand here? How does conditions like VOL = 0 V, and VOH = VDD maximized the output signal swing?
thank you so much everyone.