# variable should not be used in output port connection

I searched random verilog heirarchy to understand how to properly instantiate modules. I found one on https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_hier.html

I am getting an error saying "variable 'intsig' should not be used in output port connection"

module top_ver (q, p, r, out);
input     q, p, r;
output    reg out;
reg     intsig;

bottom1 u1(.a(q), .b(p), .c(intsig));
bottom2 u2(.l(intsig), .m(r), .n(out));

endmodule


edit 1

module top_ver (q, p, r, out, clk);

input     q, p, r ,clk;
output    reg out;
reg     intsig;
always@(posedge clk) begin
bottom1 u1(.a(q), .b(p), .c(intsig));
bottom2 u2(.l(intsig), .m(r), .n(out));
end
endmodule


## 1 Answer

Even if the c output of bottom1 is produced by a flip-flop, in top_ver you are not assigning intsig in a procedural block (an always or initial block).

Therefore you must declare intsig as a wire rather than a reg.

Regardless of whether the signal is actually produced by a flip-flop or combinatorial logic, in Verilog you declare a signal as reg when you will assign to it in a procedural block (again, always or initial) and you declare it as wire (or one of the variants like wor or wand) when you are going to assign to it in a combinatorial statement (assign or as the output of an instantiated module).

• i tried using an always block so i can have clk as an input. I am getting an error that the bottom1 and bottom2 are not defined. edit got it. it shouldn't be done inside the always block – Eris Drater Jul 15 '18 at 23:26
• You can't instantiate a module inside an always block. You should declare intsig as wire instead of reg, because you aren't going to assign to it in an always block. – The Photon Jul 15 '18 at 23:44