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I am trying to use the ethernet PHY on my Nexys4-DDR. The manual for the phy gives the following timing constraints for the RMII ports.

enter image description here

I am getting confused as to what exactly the constraints for this should be in my XDC file. For the above diagram I think I can conclude...

Input setup time  = 20 - 14 = 6ns
Input hold time   =  3ns
Output setup time = 4ns
output hold time  = 1.5ns

From this I generated the following constraints relative to clk_mac which is the 50MHz clock driving clkin.

set_input_delay -clock clk_mac -max 6.000 [get_ports {eth_crsdv eth_rxd eth_rxerr}]
set_input_delay -clock clk_mac -min 3.000 [get_ports {eth_crsdv eth_rxd eth_rxerr}]
set_output_delay -clock clk_mac -max 4.000 [get_ports {eth_txd eth_txen}]
set_output_delay -clock clk_mac -min 1.500 [get_ports {eth_txd eth_txen}]

I am unsure if I am mapping min/max to hold/setup correctly. When I ran this design with chipscope it does not look like I am getting a valid packet on the rx side. I previously had it working using no input constraints but with a 45 degree phase shifted clock. So I guess that is like an effective delay of 5ns everywhere. I also tried just setting all delays to 5ns and it started to work. How should I correctly constrain this design?

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  • \$\begingroup\$ How is your clk_mac defined? \$\endgroup\$ – DonFusili Jul 17 '18 at 14:10
  • \$\begingroup\$ It is derived from the 100mhz clock. I use a PLL. \$\endgroup\$ – chasep255 Jul 17 '18 at 15:13
  • \$\begingroup\$ So then how does your design know about the reference clock (clkin)? \$\endgroup\$ – DonFusili Jul 17 '18 at 15:14
  • \$\begingroup\$ I am the one providing the 50 mhz clock. \$\endgroup\$ – chasep255 Jul 17 '18 at 15:15
  • \$\begingroup\$ Yes, but that clock has to be routed to the exit and the delay of the data signal on the pins (which is what you specify), has to be referenced to the clock signal when it appears on the pin. Your system doesn't know about that reference yet. \$\endgroup\$ – DonFusili Jul 17 '18 at 15:23

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