I'm using an STM32L155 in a very small (0.4 mm pitch) WLCSP package (6x9 array). At this scale there is no room for traces between the balls, so the design requires HDI and/or blind vias to fanout the signals.
I'll only be using about half of the signals. I'm still early in the design process, but I am hoping to use blind vias-in-pad with a six-layer stackup. My intended stackup is
Signal, Ground, Signal, Signal, Power, Signal.
I'll be putting components on both sides of the board. I want to avoid using buried vias to save costs.
Here's my problem:
I'm using an external 32 kHz crystal to source an accurate real-time clock. One of the balls isn't accessible on the top layer (see the green signals):
These pin locations are fixed. I'll need to drop a via-in-pad from the inner pin to get access to it.
So, my question:
Since I need to use a via anyway, would it be preferable to:
Use thru-vias on each crystal pin and then place the crystal (and bias caps) on the bottom of the board, or
Drop the inner signal to layer 3 using a blind via; run it to the right, and have it come back to the surface next to the crystal?
Do something much more clever that I haven't thought of yet?
I understand that it may not matter much on a 32 kHz crystal, but I'm looking for best practices. I would have the same problem if I was using the external high-speed crystal (24 MHz); the pinout is similar.