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I'm using an STM32L155 in a very small (0.4 mm pitch) WLCSP package (6x9 array). At this scale there is no room for traces between the balls, so the design requires HDI and/or blind vias to fanout the signals.

I'll only be using about half of the signals. I'm still early in the design process, but I am hoping to use blind vias-in-pad with a six-layer stackup. My intended stackup is Signal, Ground, Signal, Signal, Power, Signal.

I'll be putting components on both sides of the board. I want to avoid using buried vias to save costs.

Here's my problem:

I'm using an external 32 kHz crystal to source an accurate real-time clock. One of the balls isn't accessible on the top layer (see the green signals):

wlcsp

These pin locations are fixed. I'll need to drop a via-in-pad from the inner pin to get access to it.

So, my question:

Since I need to use a via anyway, would it be preferable to:

  1. Use thru-vias on each crystal pin and then place the crystal (and bias caps) on the bottom of the board, or

  2. Drop the inner signal to layer 3 using a blind via; run it to the right, and have it come back to the surface next to the crystal?

  3. Do something much more clever that I haven't thought of yet?

I understand that it may not matter much on a 32 kHz crystal, but I'm looking for best practices. I would have the same problem if I was using the external high-speed crystal (24 MHz); the pinout is similar.

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  • \$\begingroup\$ I would focus my attention on the layout of the crystal, not the MCU, since most MCUs will specify for tracks "as short as possible" but some crystals demand a certain layout for performance. If the crystal doesn't specify, then I would place the crystal on the opposite side of the board, just shy of the MCU, and run a thru-via to each pin. Simple. \$\endgroup\$ – Ed King Jul 17 '18 at 23:32
  • \$\begingroup\$ Don't they have any reference design kits? For 32 kHz the most important thing is to avoid parasitic conductance to VCC or GND via contamination by no-clean flux residuals. \$\endgroup\$ – Ale..chenski Jul 17 '18 at 23:44
  • \$\begingroup\$ remotely related: How's my crystal oscillator layout? \$\endgroup\$ – Nick Alexeev Jul 18 '18 at 0:18
  • \$\begingroup\$ At such low frequencies, unless you let a one year old doodle the traces, you can often even get away with placing the crystal a meter away obviously the pcb \$\endgroup\$ – PlasmaHH Jul 18 '18 at 7:20
  • \$\begingroup\$ As @PlasmaHH says 32KHz crystals or not critical in wire length. You can use via's down and back up again and have the crystal at the top. Capacitance is critical so keep ground away and be prepared to try different capacitor values to tune the freq. to as near as possible to 32768 Hz. \$\endgroup\$ – Oldfart Jul 18 '18 at 7:42

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