0
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I'm writing an fsm which is struck between s1 and s2 and not going to next state. Even if I increase the delay after s3 ( for it to complete operation). I even observed the simulation that the data was available at that instant but the control path didn't go to s3. It starts from s0 and jumps to s2-s1-s2-s1-s2-s1........ (I already declared s0,s1,s2..,w0,w1,.... as parameters)

Please let me know where I did mistakes.

Here is my verilog code:

always@(posedge clk)begin
   if(rst)
      cstate<=s0;
   else
      cstate<=nstate;  end


always@(cstate)
begin
case({cstate})
s0:
begin
control signals // for the module instantiations enable in data path
state_indicator<=6'b000000;
end
w0:
begin 
#150;
state_indicator<=7'b000001;
end
s1:
begin 
control signals
state_indicator<=6'b000010;;
end
w1:
begin 
#10000;
state_indicator<=6'b000011;
end
s2:
begin
control signals
state_indicator<=6'b000100;
end
w2:
begin
#6000;
state_indicator<=6'b000101;
end

s3: begin
control signals
state_indicator<=6'b000110;
end
w3:
begin
#10000;
state_indicator<=7'b0000110; 
end

and I wrote

always@( cstate or start or done1)
begin
case({cstate})
s0:begin  if(start) begin nstate<=w0 ; end 
        else if(!start) 
        begin nstate<=s0; end  
        end
w0: nstate<=s1;
s1: nstate<=w1;
w1: nstate<=s2;
s2: nstate<=w2;
w2: nstate<=s3;
s3: nstate<=w3;
w3: nstate<=s4;
s4: nstate<=w4;//1delay
w4:nstate<=s5;
s5:begin  if(!done1) nstate<=s1;
else if(done) nstate<=s6; end
endcase
end
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  • 1
    \$\begingroup\$ I don't see a clock anywhere. Start using a clock. Look at other Verilog FSMs on the web for examples. \$\endgroup\$ – Oldfart Jul 18 '18 at 7:33
  • \$\begingroup\$ @oldfart sorry for not mentioning there. There is an always block which always equals cstate<=nstate if reset =0 \$\endgroup\$ – Sandeep I Jul 18 '18 at 7:42
  • \$\begingroup\$ That's not a clock. You need a clock. \$\endgroup\$ – duskwuff Jul 18 '18 at 7:58
  • \$\begingroup\$ The non-blocking assignments occur when the sensitivity list is satisfied, and you clearly have a race condition and using a static signal means they will continue to occur. Use a clock so the assignments happen at a properly defined time. \$\endgroup\$ – Peter Smith Jul 18 '18 at 12:08
  • \$\begingroup\$ Thanks everyone. I got it right. Of course I've used clock always@(posedge clk) to equal cstate=nstate. The problem is with state assignment. I've declared the delay to the state assignment in one block ( it has to wait until operation complete and proceed to next state). \$\endgroup\$ – Sandeep I Jul 18 '18 at 13:39

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