I just finished a Coursera course on hardware design (nand2tetris) and I want to take the next step and implement the design in an FPGA. Being fairly new to the hardware aspect of computing in general, I needed to clear a few questions regarding memory. In particular, I want to implement a memory design that is organized into square arrays of 16 bit wide registers. The data would be accessed by specifying an array and then either a row or column (with the goal of expediting matrix multiplication). However, I am unsure if such a design will fit into an FPGA (I believe I can afford at most a Cyclone V or something equivalent). Since GPUs can be implemented on FPGAs, there must be a more efficient way of doing this that does not require using the D flip flops in each logic element to store a bit from an individual register. If there is not, how do people handle arrays of data in parallel on FPGAs? Any information would be really helpful and since this is all a purely pedagogical exercise, pointers to learning materials on the subject are appreciated.

  • \$\begingroup\$ 1/ How big are your matrices? 2/ Matrix multiplication does not requires row AND column access for each matrix. For one you need rows for the other you need columns. \$\endgroup\$ – Oldfart Jul 19 '18 at 3:23
  • \$\begingroup\$ Ideally I would try to fit about 100×100 matrices. I was considering both column and row access because at some point I might have to left multiply a matrix and at another I might have to right multiply it, so having the flexibility to do it without having to transpose it would be nice. \$\endgroup\$ – Guacho Perez Jul 19 '18 at 4:54

Your 'most limited resource' is likely going to be the number of multipliers on the FPGA.

Your matrix multiplication logic will then consists of a stream of numbers read from a source, fed into a bundle of multipliers and the result stored again.

Two-dimensional access is easiest implemented using register albeit it also uses a lot of logic to select the outputs. I have implemented a two-dimensional memory using standard (one dimensional) memory chips but that was patented. I think you will just need to spend some cycle 'rotating' the matrix. Or be clever how you write the result. You might even consider storing each matrix twice.

I am more concerned about precision.
I have no idea what your numbers are, but I do recollect colleges at Delft University about the problems with maintaining precision when repeatedly using floating point numbers. In your case it will be worse because the multiplier in an FPGA has only a limited number of integer bits. Unless you want to implement massive parallel floating point multiplication.

  • \$\begingroup\$ Does this memory design have a name that I can look up? Where can I find out more? \$\endgroup\$ – Guacho Perez Jul 19 '18 at 6:27
  • \$\begingroup\$ No, it does not have a name. I can't tell you more. (non-disclosure etc.) \$\endgroup\$ – Oldfart Jul 19 '18 at 6:32
  • \$\begingroup\$ You did not mention what FPGA you used. Is it possible to implement what I described in a chip like the Cyclone V? \$\endgroup\$ – Guacho Perez Jul 19 '18 at 6:37
  • \$\begingroup\$ It was in an ASIC, not an FPGA (Look at my profile :-) \$\endgroup\$ – Oldfart Jul 19 '18 at 6:40
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    \$\begingroup\$ Yes, you can implement it on an FPGA, but I think your focus is wrong. I suggest you start with normal matrix multiplication and with the experience of that re-assess how to make it more efficient. \$\endgroup\$ – Oldfart Jul 19 '18 at 6:54

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