I'm currently designing a 4-layer PCB for a SOC (Allwinner A33 to be precise, 0.8mm-pitch BGA) with one DDR3 chip. Per DDR3 routing requirements, the traces need to have 50-ohm impedance. Also, they need to fit between BGA pads and breakout vias, which limits the trace width to max. 5mils.

To achieve 50-ohm impedance with a 5-mil microstrip, the dielectric layer needs to be about 3-4mil thick. Currently, I'm preparing to manufacture a few prototype pieces, and I'm having trouble finding a fabrication service online which would offer the required stackup.

So, the question is: how do people get such prototypes manufactured?

  • \$\begingroup\$ Many PCB prototyping fabs in china have the option for controlled impedance. For example, I know that pcbway.com does (in their "additional options" section). It costs a little extra, but is still fairly reasonable \$\endgroup\$
    – BeB00
    Commented Jul 19, 2018 at 9:45
  • \$\begingroup\$ I've discussed the controlled impedance option with one chinese manufacturer. Their explanation was "Our engineer will change your trace width", which means making the traces 10mil :( \$\endgroup\$ Commented Jul 19, 2018 at 10:12
  • 2
    \$\begingroup\$ For some reason most of the cheap fabs use a default 4 layer stackup that is pretty useless for modern designs, the outer dielectric thicknesses are just way too large. This is easily fixed by specifying a custom stackup but that will usually take you out of the very cheap service category. \$\endgroup\$
    – Dan Mills
    Commented Jul 19, 2018 at 10:23

1 Answer 1


You have some things to consider in the layout process. It is common to use the required narrow trace (you indicated 5 mil) to breakout from the BGA pin field. As soon as you clear the pin field you expand the trace width to achieve the desired impedance for the route over to the DDR3 chip. Of course that routing depends upon your stack-up and calculated trace width to achieve the needed 50 ohm impedance. The other considerations relate to total available area to route and any necessary length matching that may be required.

Depending upon the DDR3 chip footprint it may be necessary to again neck down the trace a bit of there is a pin field to route through to the final pad.


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