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I made a window function generator IP in Xilinx Vivado. It works well in the simulation. When I tried to implement for Zedboard, it gives a timing error. The error is caused by Cordic IP used for cosine function.

This is a part of the timing report:

Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -2.636ns  (required time - arrival time)
  Source:                 design_1_i/axi_window_top_0/U0/design_inst/design_1_i/cordic_2QN_1QN/U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_phase.gen_phase_cr/gen_rtl.gen_reg.d_reg_reg[36]/C
                            (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            design_1_i/axi_window_top_0/U0/design_inst/design_1_i/cordic_2QN_1QN/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/data_slice/x_plus_y_shift/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/i_no_async_controls.output_reg[34]/D
                            (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_fpga_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
  Data Path Delay:        12.482ns  (logic 6.040ns (48.392%)  route 6.442ns (51.608%))
  Logic Levels:           11  (CARRY4=10 LUT1=1)
  Clock Path Skew:        -0.062ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.725ns = ( 12.725 - 10.000 ) 
    Source Clock Delay      (SCD):    3.016ns
    Clock Pessimism Removal (CPR):    0.229ns
  Clock Uncertainty:      0.154ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.300ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

It goes like this.

How can I fix this issue? Should I adjust some parameters of Cordic IP or should I run multiple Cordics in parallel?

My Cordic IP configurations:

Architectural Configuration: Parallel
Pipelining Mode            : Maximum
Data Format                : SignedFraction
Phase Format               : Scaled Radians
Input/Output Width         : 32
Round Mode                 : Trunctate
Iterations                 : 0 (Default)
Precision                  : 0 (Default)
Coarse Rotation            : Yes
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  • \$\begingroup\$ I would start with: 1/ Do you really need a 32-bit result? 2/ Do you really need 100MHz? Otherwise you best solution is to run two in parallel at 50MHz. \$\endgroup\$ – Oldfart Jul 19 '18 at 15:37
  • \$\begingroup\$ According to the official document (page 35), it should work even at 200MHz (32-bit parallel configuration on Spartan-6). Does your FPGA belong to an older family? \$\endgroup\$ – ahmedus Jul 20 '18 at 8:49

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