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I've been chasing an issue in a 3-Phase BLDC inverter for some time now. The problem manifests itself as high current and voltage sense noise at high DC bus voltages, irrespective of the load on the inverter.

I've broken the design down into its smallest elements and from what I can tell, the voltage at the switching node (source of high side MOSFET) remains at the DC Bus voltage long after the high side MOSFET is off. This measured voltage is most likely stored energy in a bootstrap capacitor on my driver or the capacitance of the MOSFET.

When the low side MOSFET is switched on, I get fairly large oscillations at the low side gate and drain. This also appears as large currents in the current measurement system.

About the design:

  1. 3-Phase BLDC Inverter, capable of 310V DC Bus, however for this exercise testing at 24VDC.
  2. MOSFETS are STF10N60DM2
  3. Gate Driver is 6EDL04N06PT
  4. PWM Control, etc is generated from TMS320F28069F MCU

I've prepared an example schematic showing a a single pair of MOSFETS as per the image below, and I've annotated the colors of the scope measurement channels.

Basic Schematic

I've captured the relevant issue on the scope in the image below, however there are a few things to note.

  1. Blue = Upper Gate measured at the MOSFET
  2. Green = Upper Source Measured at the MOSFET
  3. Pink = Lower Gate, Measured at the MOSFET
  4. Yellow = Switching Node (Identical to Green but overlaid on Blue)
  5. D4 = High side PWM Signal from MCU, D5 = low Side.

In this capture there is NO LOAD connected to the design, and the PWM is operating in open loop control mode. I have very similar waveforms, irrespective of whether I have No Load, a Resistive Load or an Inductive Load connected.

There is a ~500ns propagation delay through the driver, the PWM dead-band is at 800ns and I've annotated with grey lines the PWM input versus MOSFET switching edge.

As for the probing techniques, I have SMA connectors on the hardware at the appropriate measurement points. Even if I use a standard scope probe and 100mm ground clip, I still get the same measurement. Using these two diverse measurement methods, and achieving the same measurements I'm certain the noise is present in the circuit and not a measurement artefact.

Scope Capture 01

What I have tried:

  1. Ferrite beads in the gate drive path.
  2. Various combinations of Gate slew control resistors
  3. 1K resistor between GS on each FET
  4. 100nF to 10uF bootstrap capacitors
  5. Different types of MOSFETS

My Questions:

  1. Is what I am seeing on the Yellow Trace (Switching Node) correct? I think I should see the yellow trace go low after upper MOSFET is off.
  2. When the lower MOSFET switches on (Pink Trace) I get a lot of disturbance, (this is actually massive at 310VDC). What is the cause of this?

Any help would be greatly appreciated.

Update 1, 2018-07-25:

Top Layer Image showing gate driver, low side gate trace (its a 0.8mm track, ~35mm long). Pink and Yellow measurement points shown. Red triangles are gate driver GND attach points. enter image description here

Bottom layer image showing FET's, DC Bus, GND and decoupling caps. Please note there are additional layers of copper in this design where GND and DC_BUS are duplicated, hence the via stitching. enter image description here

Note: In this design we are using our own current sense resistors on each phase, and NOT using the current trip feature of the gate driver. This means that Pin 12 and Pin 13 (VSS and COM) are linked together.

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  • \$\begingroup\$ I know you said you tried different loads. But with no load, there is no reason for the switch node to go low until the lowside FET turns on. I definitely don't like the gate waveform you are seeing on the low side. \$\endgroup\$ – mkeith Jul 20 '18 at 7:20
  • \$\begingroup\$ @mkeith, yeah thanks, I should have clarified the no-load situation like you mentioned. \$\endgroup\$ – SafetyLok Jul 20 '18 at 7:25
  • \$\begingroup\$ You say you expect the switch node to go low as soon as the high side gate is off. But that is not a correct expectation when there is no load. When both high side and low side are off, the switch node is floating. So it does not go low until the low side turns on. \$\endgroup\$ – mkeith Jul 20 '18 at 14:55
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    \$\begingroup\$ The disturbance you see when the low-side switch turns on seems to be caused by the drain-gate capacitance of the low side FET interacting with some parasitic inductance. As the gate goes up, all is well. But as soon as it reaches what SHOULD be a plateau, it starts to ring or resonate. I think playing with the low-side gate elements might allow you to eliminate it. Try connecting the gate directly to the driver. They try resistor only (like 10 Ohms). Etc. You shouldn't need two resistors and a diode since your gate driver already has a dead time. \$\endgroup\$ – mkeith Jul 20 '18 at 15:01
  • \$\begingroup\$ Also, if you haven't already, I would suggest that you engage with Infineon field applications engineers (FAE). You obviously know what you are doing, and have formulated your question very thoroughly. I would think Infineon would be very interested in helping you. \$\endgroup\$ – mkeith Jul 20 '18 at 19:03
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It looks like a straight drive problem to me. The gate and drain curves have a relationship that looks reasonable, so I think you are getting a good measurement. The only thing to do is to decrease the drive impedance. You can reduce the inductance in the gate drive lines by making the path as short and fat as possible; remove the coupling to the current path by keeping the gate drive path from laying on top of the power and ground planes; but to really improve you will have to get a more muscular driver to overcome the negative feedback from the gate-drain capacitance. This symptom will become more pronounced with the higher voltage because the higher dv/dt will mean more voltage on the gate. You can shop for a FET with low gate capacitances, but these generally have higher "on" resistance.

As I said earlier, this is not a terrible switching waveform; you can probably run a motor with moderate current but you will have losses that will heat up the FET. However if you are running high currents, you have probably noticed that "real" gate driver IC's often sport output currents in the 5 ampere range.

One other thing you must do in any case is to provide a big low ESR (ceramic not electrolytic) decoupling cap for your drive circuitry. There must be an adequate charge reservoir to provide that instantaneous ampere or two that you will need to overcome the dv/dt coupling effect. I can't tell if you have a 2.2 uF ceramic from your schematic, but I'm guessing you do. If you do put in FET drivers, the capacitance is necessary.

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  • \$\begingroup\$ The more I think about it, this gate driver has been giving me hell from day 1. The output currents are only 0.25A, and that is across the entire product line, so one would think its suitable to drive a simple FET. I have low ESR 0.1, 2.2, 10 and 47uF caps at the VCC pin of the driver. I will try one more board with TI UCC27714 drivers, however the downside is I need additional overlap protection. Cheers! \$\endgroup\$ – SafetyLok Jul 25 '18 at 0:34

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