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My problem is about AND-gate when its inputs are open. I want to know: What is the output when inputs are open? The output is Z (open) or 0?

What is your idea about this AND-gate transistor structure?

two transistor AND gate structure

(Image source)

My answer to the above structure is that the output is 0 when the two inputs are open, or at least one of them is 0.

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The answer depends on the design of the AND gate.

A traditional TTL gate will treat an unconnected input as a logic high, so the AND gate with two unconnected inputs will output high.

For a CMOS gate, the result is much less predictable. The unconnected input might drift either high or low, depending on nearby static fields. Worst case it drifts to an intermediate voltage and only partially switches the output, leading to excess heating of the gate. Or the output could oscillate between high and low (again leading to heating up the circuit).

A high-Z output is unlikely in either case, although it could be the result for something like a simple wired diode logic.

Edit:

Th 2-transistor AND gate at your linked site is neither a traditional TTL design nor a CMOS design.

enter image description here

This circuit will treat an unconnected input as low, since it is current flowing in to the transistor bases that defines a "high" input for this circut.

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  • \$\begingroup\$ as a system level designer(logic design) should i know about the structures of gates to design a system? \$\endgroup\$
    – user194071
    Commented Jul 20, 2018 at 20:44
  • \$\begingroup\$ Yes, you will have to know something about the underlying technology. You should probably never leave an input unconnected. But you will often need to know the propagation delays of your gates, the fan-out capability, the input leakage currents, etc. \$\endgroup\$
    – The Photon
    Commented Jul 20, 2018 at 20:49
  • \$\begingroup\$ I disagree. As a logic designer (logic as something mathematical) you shouldn't need to know about the technology used, it could be vacuum tubes or relays for all you know, the logic aspect will still be the same. Note that it such an abstract level an unconnected input can't exists, so the problem you asked about doesn't arise. \$\endgroup\$ Commented Jul 20, 2018 at 21:40
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    \$\begingroup\$ @WoutervanOoijen, if you want to define it that way, sure. But then nobody I know is strictly a logic designer. They're interested in designing digital circuits that work, not mathematical abstractions. \$\endgroup\$
    – The Photon
    Commented Jul 20, 2018 at 22:06
  • \$\begingroup\$ But then the guys I know are mostly doing very high speed, relatively low complexity, designs. \$\endgroup\$
    – The Photon
    Commented Jul 20, 2018 at 22:07
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For the simple two transistor gate shown iin your link, the output will be Low when either input is open - if a transistor has no base current, it will also have no collector current.

In a real AND gate, the result of an open input will depend on the actual circuit of the gate, which will be more complex than two transistors.

For bipolar TTL logic, the input will source current, so will appear as a logic High if unconnected.

For CMOS logic, the inputs are FET gates which are very high impedance - in that case, an unconnected input may wander randomly between High and Low.

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