3
\$\begingroup\$

In a simple control unit using microcoded sequencing, I use a ROM to store the sequences of control signals. The instruction forms the top 8 bits of the ROM address, and the bottom eight bits are formed by a counter that is incremented on the falling edge of the clock.

The zero address of the ROM contains the signal to load an instruction into the instruction register, thus pointing the ROM to that address and outputting the data there in order. After the instruction is completed, the ROM will output bits to clear the instruction register and microcode counter, restarting the whole process. When these bits are set high, the ROM address is instantly reset and the bits go low immediately.

My goal is to implement this circuit using 7400 series logic and an EEPROM, but I am suspicious that my method of using the ROM data to asynchronously reset its own address registers will introduce a race condition or otherwise invalid state. Is this method acceptable. If not, what is the appropriate way to do this?

Logisim circuit diagram for a microcode control store.

\$\endgroup\$
4
\$\begingroup\$

I assume you are talking about an a-synchronous reset here.

The safest way is to pass the reset through a register. That way it will remain asserted even if the input to the register goes away.

As often the devil is in the detail:

  1. The register gives a delayed reset thus you might have to make the reset active 1 clock cycle earlier. (Depends how your circuit works)

  2. You then have to AND the reset with the not-clock so it is active only during the first half of the clock cycle. (As you are doing now) If you don't do that you will have a different race condition: your reset goes away at the same time as your clock rises.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.