As far as I know there are two major buses - AMBA/AXI and Wishbone. While AMBA/AXI has proven itself in almost every ARM chip, I didn't find some numbers for Wishbone. Are there any benchmarks or real (ASIC) implementations of Wishbone?
Bus requirements: - patent/license free; - can connect endpoints with arbitrary bit sizes (e.g. 64 bit to 32 bit); - fast (can be used to interface ddr3 controller)