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I have a question regarding the behaviour of a MCU's GPIO pins when configured in a certain way in hardware and software. In this case I am using a dsPIC33EP, but I believe this question is generally applicable to MCUs with push/pull outputs. At certain points in the circuit I am developing I need a pull-up resistor on the line to ensure that the connected chip has a hardware default state (in this case HIGH) even when the PIC has been turned OFF. If I pull up this line to a voltage equal to or greater than the power supply of the PIC (3.3V) but the PIC outputs a HIGH at slightly-below whatever this voltage level is... what happens to the output of the PIC?

I am using a 5V-tolerant pin on the PIC, which in the electrical specifications guarantees that it will tolerate up to 3.6V when the PIC is off, so that is not an issue. What I am uncertain about is how the PIC handles a (small) over-voltage condition on an output through a pull-up resistor.

If Vp is greater than VOH, will there be damage done to the chip?

GPIO Setup

On a side note, I have considered some solutions to this problem and will likely set up these outputs in software to behave as open-drain types. My question is regarding the feasibility of doing it using PUSH-PULL outputs, but if anyone has any other simple solutions to offer for application's sake, please feel free!

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  • \$\begingroup\$ Since you are using 3.3 V for the PIC, why does it output 2.4 V as logic high ? \$\endgroup\$ – Long Pham Jul 23 '18 at 14:24
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    \$\begingroup\$ It does not consistently output a 2.4V high per se, but the datasheet specifies that with a 3.3V supply, this is the minimum guranteed output level. The main idea here is that the pull-up voltage COULD be higher than the output voltage, in some cases. \$\endgroup\$ – WMW Jul 23 '18 at 14:28
  • \$\begingroup\$ It's the worst case value when the IO sinks/sources quite alot of current. \$\endgroup\$ – Long Pham Jul 23 '18 at 14:33
  • \$\begingroup\$ Yes, I imagine that is correct. \$\endgroup\$ – WMW Jul 23 '18 at 14:34
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What your solution will do when the PIC is powered down depends on the pin type (some are 5V tolerant which means there is no diode to the power rail).

Looking at the absolute maximum ratings for 5V tolerant pins shows a maximum of 3.6V when Vdd < 3.0. Whether this holds true when powered off is not specifically answered, but as it appears to be an electrostatic stress rating, I would suspect so.

For normal operation, the output voltage depends on load as you will see in the output driver specifications. Although the minimum output voltage that is guaranteed is 2.4V, the more likely output voltage will be far closer to Vdd for an interface to a high impedance input.

I notice that you pull up to 3.4V - is that because your module has true CMOS inputs? (transitions at 1/3 and 2/3 Vdd).

Edit: The dsPIC33EP absolute maximum rating for Vdd > 3.0V on a 5V tolerant pin is 5.5V, so I don't really see an issue if you don't exceed that.

Some current will flow into the line if the pullup exceeds Vout, so the the PIC output is high but lower than the pullup, then the pullup will tend to try and backfeed the pushpull output. Provided you do not turn on the body diode of the upper FET (a diode drop), I would not be particularly concerned.

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  • \$\begingroup\$ Thanks for the input! As stated in the question, the state of the circuit when the PIC is powered down is not a concern and has been verified. The pullup voltage comes from a source (guaranteed to be always on, essentially) that has some slight fluctuation to it. The concern is that in SOME cases, the pull-up voltage on the line will be higher than the PIC's output voltage. At this point, I am unsure of how the PIC handles this. \$\endgroup\$ – WMW Jul 23 '18 at 14:31
  • \$\begingroup\$ I don't know this still hold true for the PICs but STM32's 5V-tolerant IOs have ESD protection diode. \$\endgroup\$ – Long Pham Jul 23 '18 at 14:37
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Here is common protection method for GPIO:

schematic

simulate this circuit – Schematic created using CircuitLab

If you feed IOs with voltage exceeding VDD plus diode forward voltage (3.3 + Vf = 3.6, this is the max rated input voltage), the diode will start to clamp and maintain acceptable voltage.

So the GPIO can handle whatever input voltage, as long as, input current is limited (by current limiting resistor, of course).

Those ESD diodes can only withstand few mA, say, 5 mA (I took this value from STM32 MCU datasheet), you can calculate the minimum resistor value with this rough formula:

$$R_{limit} = \frac{V_{input} - VDD}{5 mA}$$

You can even feed mains voltage to GPIO (if you want) if it's protected by proper resistor.


Note: the clamp only works if there is the presence of supply voltage for the GPIO.

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  • \$\begingroup\$ Great info! This is a great scheme for GPIO input protection. However, my question is intended to explore a situation where the PIC has an output with a higher voltage applied to it, causing reverse current flow INTO the output. In this case, an output sinking current is the concern. Thanks for contributing! \$\endgroup\$ – WMW Jul 23 '18 at 16:30
  • \$\begingroup\$ I should have mentioned this is internal ESD protection diode but you can add external clamp just to be sure. \$\endgroup\$ – Long Pham Jul 23 '18 at 16:53
  • \$\begingroup\$ Hmmm, good question. \$\endgroup\$ – Long Pham Jul 23 '18 at 16:57
  • \$\begingroup\$ I think it will be ok, as long as the pullup resistor isn't so small. \$\endgroup\$ – Long Pham Jul 23 '18 at 17:27

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