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I have created a differential channel and was testing the channel with simple testbench to check the eye diagram. Now I know the channel performance is very bad (It of several PCB transmission lines, Via & Stubs, and Packaging model). But, I am curious while simulating channel performance, I get negative eye density while checking the eye diagram after the channel which is for me unusual. My channel can be very bad as it is not well matched to 100 ohms. But keep those aside, how can an eye density be negative? what does that mean? If the channel is poor, the can be closed more which I know, but this thing is completely new to me. Can you explain why has it happened (Eye density negative) and what does it mean by negative? I know I can improve it with an improved channel.

Note: I have done the simulation in ADS.

Test Bench enter image description here

Eye Diagram: enter image description here

Channel S-parameter (Log scale: X-axis) enter image description here

TDR Differential Impedance: enter image description here

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    \$\begingroup\$ Negative eye density is reported where in your pictures? \$\endgroup\$ – Andy aka Jul 23 '18 at 14:35
  • \$\begingroup\$ @Andyaka sorry for my terminology. I have never experienced this kind of problem of shifting the eye diagram in negative voltage, I thought maybe this is somewhat negative eye density. \$\endgroup\$ – aguntuk Jul 23 '18 at 19:21
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Can you explain why has it happened (Eye density negative) and what does it mean by negative?

This is simply DC bias of Tx output and Rx input after coupler medium.

Often differential drivers have a common mode voltage other than 0V. While Current Mode Logic (CML or ECL)often uses a negative supply for a current sink with Vcm=-ve for the Rx comparator.

Here we are dealing with very high speeds and the channel has a very good filter, so you probably cannot improve it as the output is better than the input.

Why? you never asked, but here is the answer.

Your channel has a BPF shape peaking at 30GHz with a -3dB BW from

1.3 to 6GHz (-3dB = 0.707 * Vmax ~ 0.35=0.245)

We expect the rise time from 10 to 90% Tr=0.35/BW.

Tx ~ 20 ps , Rx ~ 100 ps while the symbol interval is 100 ps so you expect attenuation of the eye as the rise time must be < 1/2 the symbol period to reach 100% for full swing and 100% eye opening if there was no noise, but noise is present on all.

The Tx signal is 2x the Rx signal mean P-P voltage and AC coupled around 0.3Vdc. So lets examine the Eye in relative terms of eye height to mean symbol hi/lo levels pk-pk.

SNR is improved

Tx "1" = 0.54 . . . . . Rx "1" = -0.075
Tx "0" = 0.046 . . . . . Rx "0" = -0.337
height= 0.226 . . . . . height = 0.104

"1-0"/height = 1.9 = ratio = 0.262 /0.104= 2.52

Eye Tx SNR = 5.6 dB
Eye Rx SNR = 8 dB

When operating at such low SNR this can often lead to a (Bit Error Rate ) improvement of 1 decade /dB so a 2.4dB improvement is significant like going from 1e-6 to 2e-8 BER.

I am assuming the signal and noise is constant and the channel filter is a design option, so the amplitude jitter has been reduced but the horizontal jitter has increased at the symbol crossings {X}

The signal to noise has actually improved from 1.9 to 2.52 even though the width of the eye has closed. The 3nd output is same as 2nd so this ideal.

This means the input signal noise was wider than the channel BW and the filter is ideal so that it does not cause inter-symbol-interference for 001100 and 010101 or 00100 or 11011 patterns. There is some group delay distortion in the channel which is not shown but obvious from the Rx eye closure width..

Channel filter type

A better channel will have a different group delay response with no ISI (Inter-symbol Interference) A similar BPF curve but ring at the symbol interval (raised Cosine response = ideal)

But if you used a narrower BW filter the eye width would closer more at the slight improvement of eye height jitter reduction, so depending on your discriminator type, this is close to ideal. Some only sample the middle of the eye with a PLL sync clock, others more complex integrate the energy during the entire symbol and dump and alternate to support high speed. THis can make a difference in terms of SNR vs BER probability when shown on a log-log scale.

Added TDR

The response shows some negative blips from slightly higher capacitance at some geometric change in the path at 2.1ps and 3.4ps that is from a slightly lower localized edge gap (higher C, lower Z , followed by an inductive path to a high load resistance resulting in 40% higher voltage. Then stable after 6ps . This impedance mismatch results in an additional +/-6ps of jitter, although from the coupler schematic and frequency response, thus helps to reduce amplitude noise. Better phase noise can be achieved by matching load impedance to source with s11>15dB.

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  • \$\begingroup\$ Thanks for your detailed description. The TX output Eye diagram is actually not solely TX output, it also contains reflection of channel as my channel is not good (from the s-parameter and TDR impedance graph, which I added later in the question). And I have used ADS generic TX and RX here and, in the RX, no equalizer is used. Moving to your analysis, you said my channel is somewhat good as per decade SNR is improved. I still have some confusion about shifting the eye in the negative voltage region. Is that good or bad? How to characterize the figure of merit when it shifts to negative region? \$\endgroup\$ – aguntuk Jul 23 '18 at 21:36
  • \$\begingroup\$ Disregard DC bias because of circuit details. E.g. differential signals. Or some DC ref. \$\endgroup\$ – Sunnyskyguy EE75 Jul 23 '18 at 21:40
  • \$\begingroup\$ Perhaps your coupler outputs are reversed polarity?? \$\endgroup\$ – Sunnyskyguy EE75 Jul 23 '18 at 22:00
  • \$\begingroup\$ The channel here shown is made up of differential Transmission lines and passive model of via/stub....so polarity should not be an issue...but it is true that the transmission line delay, channel performance is bad. I want to know why the voltage has been reversed. If I improve the channel, I know eye diagram will also improve. \$\endgroup\$ – aguntuk Jul 24 '18 at 10:27
  • \$\begingroup\$ @aguntuk if differential there is a complementary signal or an inverted input somewhere. DC bias is not a reflection \$\endgroup\$ – Sunnyskyguy EE75 Jul 24 '18 at 11:36
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To answer the question in your title,

What does it mean if eye diagram voltage (0 and 1 level) goes negative?

You are looking at a system with differential signalling.

A differential signal has a negative voltage if the complementary node is at a higher potential than the "true" node. Said another way, for a differential signal \$V\$ composed of two signals \$V_p\$ and \$V_n\$, the differential signal is negative if \$V_n > V_p\$.

I get negative eye density while checking the eye diagram

I don't see any sign of negative eye density in your diagrams.

You have positive eye density at negative voltages. That's not the same as negative eye density.

Negative eye density would mean that a negative number of traces passed through a point in the diagram, which is simply not possible.

I can think of cases where a certain analysis technique would produce a graph showing negative eye density due to noise and the limitations of the analysis technique, but that doesn't apply to your situation.

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  • \$\begingroup\$ Thanks a lot for your answer. sorry for my terminology. I have never experienced this kind of problem of shifting the eye diagram in negative voltage, I thought maybe this is somewhat negative eye density. So, positive eye density at negative voltages means what? I mean how to characterize the figure of merit here for this eye density? \$\endgroup\$ – aguntuk Jul 23 '18 at 19:56
  • \$\begingroup\$ Positive eye density at a negative voltage means that sometimes the voltage is negative at that time offset from the start of the bit period. This should be expected because Vn > Vp is exactly how you'd represent a logic 0 for a 2-level differential signal. \$\endgroup\$ – The Photon Jul 23 '18 at 20:25

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